Case Study 2: Building a Quantum Computer — Hardware Challenges

Overview

Building a quantum computer is one of the most ambitious engineering projects in history. Every qubit technology must simultaneously achieve excellent isolation from the environment (to preserve coherence), strong controllable interactions between qubits (to perform gates), and high-fidelity readout (to extract results) — requirements that often conflict with each other. This case study examines the concrete engineering challenges behind the two leading qubit platforms: superconducting transmons and trapped ions.

Part 1: The DiVincenzo Criteria

In 2000, David DiVincenzo articulated five criteria that any physical system must satisfy to function as a quantum computer:

1. A scalable physical system with well-characterized qubits. The system must have at least two distinguishable quantum states that form the qubit, and it must be possible to add more qubits.

2. The ability to initialize the state of the qubits to a simple fiducial state. Typically $|000\ldots0\rangle$. The initialization fidelity must be very high.

3. Long decoherence times, much longer than the gate operation time. The ratio $T_2/t_{\text{gate}}$ — the number of gates that can be executed before decoherence destroys the quantum information — must be large (ideally $> 10^4$ for error correction).

4. A "universal" set of quantum gates. The ability to implement an arbitrary unitary transformation on the qubits, to arbitrary accuracy, using a finite set of primitive gates.

5. A qubit-specific measurement capability. The ability to measure each qubit individually with high fidelity, projecting it onto the computational basis.

DiVincenzo also added two criteria for quantum communication (the ability to interconvert stationary and flying qubits, and to transmit flying qubits between specified locations), but the five above define the minimal requirements for quantum computation.

Every qubit technology can be evaluated against these criteria. No platform perfectly satisfies all five, and the relative strengths and weaknesses drive the competition between architectures.

Part 2: Superconducting Transmon Qubits

The Physics

A superconducting qubit is a macroscopic quantum system — a tiny electrical circuit, about 300 micrometers across, fabricated on a silicon chip using lithographic techniques borrowed from the semiconductor industry.

The key component is the Josephson junction: two superconducting electrodes separated by a thin ($\sim 1$ nm) insulating barrier (typically aluminum oxide). Quantum tunneling of Cooper pairs through the barrier creates a nonlinear inductance that, when combined with a capacitor, forms an anharmonic oscillator.

The Hamiltonian of a transmon (the most common type of superconducting qubit, developed by Koch et al. at Yale in 2007) is:

$$\hat{H} = 4E_C(\hat{n} - n_g)^2 - E_J\cos\hat{\varphi}$$

where $E_C = e^2/(2C_\Sigma)$ is the charging energy, $E_J$ is the Josephson energy, $\hat{n}$ is the number of Cooper pairs, $\hat{\varphi}$ is the superconducting phase difference, and $n_g$ is a gate charge offset.

The transmon operates in the regime $E_J/E_C \gg 1$ (typically $\sim 50$), which makes the energy levels insensitive to charge noise (a major decoherence source). The lowest two energy levels $|0\rangle$ and $|1\rangle$ form the qubit, with a transition frequency typically in the range 4-6 GHz.

The anharmonicity — the difference between the $|0\rangle \to |1\rangle$ and $|1\rangle \to |2\rangle$ transition frequencies — is typically 200-300 MHz. This anharmonicity is what makes the two-level approximation valid: microwave pulses tuned to the $|0\rangle \to |1\rangle$ frequency do not excite transitions to $|2\rangle$.

Engineering Challenges

Challenge 1: Operating temperature. Superconducting qubits must be cooled to approximately 15 millikelvin — colder than outer space — using dilution refrigerators. At this temperature, the thermal energy $k_BT \approx 1.3 \times 10^{-6}$ eV is much smaller than the qubit energy gap $h\nu \approx 2 \times 10^{-5}$ eV (for a 5 GHz qubit), ensuring that the qubit is in the ground state with high probability.

Dilution refrigerators are large (about the size of a telephone booth), expensive ($\sim \$500{,}000$-$\$1{,}000{,}000$), and have limited cooling power at the lowest temperature stage ($\sim 10$ $\mu$W at 15 mK). This limits the number of control lines and the total heat dissipation, which in turn limits qubit count.

Challenge 2: Coherence. The two key decoherence times are $T_1$ (energy relaxation time — how long before $|1\rangle$ spontaneously decays to $|0\rangle$) and $T_2$ (dephasing time — how long before the phase relationship between $|0\rangle$ and $|1\rangle$ is lost). For current transmons, $T_1 \sim 50$-$500$ $\mu$s and $T_2 \sim 20$-$300$ $\mu$s.

The dominant decoherence mechanisms include: - Two-level systems (TLS): Defects in the amorphous oxide layers of the junction and the chip surface create parasitic two-level systems that couple to the qubit. - Quasiparticle tunneling: Non-equilibrium quasiparticles (broken Cooper pairs) tunnel through the junction, causing energy relaxation. - Photon shot noise: Residual thermal photons in the readout resonator cause dephasing.

Improving coherence requires exquisite materials science: cleaner substrates, better junction fabrication, improved electromagnetic filtering, and radiation shielding (cosmic rays can break Cooper pairs and temporarily decohere entire chip regions).

Challenge 3: Gate fidelity. Single-qubit gates are implemented by applying microwave pulses at the qubit frequency. The pulse shape (amplitude, frequency, and duration) must be precisely calibrated to rotate the qubit state by exactly the desired angle. Current single-qubit gate fidelities exceed 99.9%.

Two-qubit gates are more challenging. The most common approach uses a tunable coupler between two transmons, activated by bringing the qubits into resonance (or near-resonance) for a controlled duration. Current two-qubit gate fidelities are 99.0-99.7%, with gate times of 30-100 ns.

Challenge 4: Crosstalk and frequency crowding. As the number of qubits increases, the microwave control signals intended for one qubit can inadvertently affect neighboring qubits. This crosstalk is particularly severe for qubits with similar frequencies. Managing the frequency layout of a large chip — ensuring no two neighboring qubits have frequencies that interfere — becomes increasingly difficult beyond $\sim 100$ qubits.

Challenge 5: Wiring. Each qubit requires multiple control lines (drive, flux bias, readout) that run from room-temperature electronics down to the 15 mK stage. For a 1,000-qubit chip, this means thousands of coaxial cables, each carefully thermalized at multiple temperature stages. This "wiring bottleneck" is a major engineering challenge.

The State of the Art (2025)

IBM's roadmap targets 100,000 qubits by 2033. Google has demonstrated error correction below the break-even point with their surface code experiments. The field is actively pursuing modular architectures (connecting multiple smaller chips via microwave or optical links) to circumvent the wiring bottleneck.

Part 3: Trapped Ion Qubits

The Physics

A trapped ion qubit is a single atom — typically ytterbium-171 ($^{171}$Yb$^+$) or calcium-40 ($^{40}$Ca$^+$) — held in an electromagnetic trap and manipulated with lasers. The qubit is encoded in two long-lived internal states of the ion.

For $^{171}$Yb$^+$, the qubit states are the two hyperfine levels of the ground-state manifold:

$$|0\rangle = |F=0, m_F=0\rangle, \quad |1\rangle = |F=1, m_F=0\rangle$$

separated by 12.6428 GHz. These states are "clock states" — first-order insensitive to magnetic field fluctuations — giving them intrinsically long coherence times.

The ions are confined in a Paul trap (radio-frequency quadrupole trap) or a Penning trap (static electric and magnetic fields). In a linear Paul trap, the ions form a one-dimensional chain, like beads on a string, with inter-ion spacing of 2-5 $\mu$m.

Two-qubit gates exploit the shared motional modes of the ion chain. When two ions are illuminated with laser beams, the light field can entangle the ions' internal states via their common motion. The Molmer-Sorensen gate and the geometric phase gate are the two most common implementations.

Engineering Challenges

Challenge 1: Scaling. A single chain of trapped ions becomes unstable beyond about 50-100 ions (the radial confinement weakens as the chain gets longer, eventually allowing ions to "zigzag" out of a linear configuration). Scaling to thousands of qubits requires one of two approaches:

• Shuttle-based architectures: Ions are physically moved (shuttled) between different trapping zones on a chip. This is the approach pursued by Quantinuum. The challenge is performing the shuttle fast enough that it does not introduce decoherence, while maintaining precise control over thousands of electrodes.

• Photonic interconnects: Each ion is entangled with a photon, and the photons from different trapping zones are interfered to create entanglement between remote ions (similar to the Delft NV center experiment). This is the approach pursued by IonQ. The challenge is the low success probability of photonic entanglement ($\sim 10^{-4}$ per attempt).

Challenge 2: Gate speed. Two-qubit gates in trapped ions take 100-500 $\mu$s — about 1,000 times slower than superconducting gates. This is because the entangling interaction is mediated by the mechanical oscillation of the ion chain, which has a frequency of 1-5 MHz (compared to GHz frequencies for superconducting qubits). The slow gate speed means that even though trapped ions have much longer coherence times, the number of gates per coherence time ($T_2/t_{\text{gate}} \sim 10^6$) is comparable to superconducting qubits ($T_2/t_{\text{gate}} \sim 10^3$-$10^4$).

Challenge 3: Laser complexity. Each ion requires multiple precisely aligned and stabilized laser beams for state preparation, gate operations, and readout. The laser systems are large, expensive, and sensitive to environmental perturbations (vibration, temperature drift). Some groups are pursuing integrated photonics — coupling laser light into waveguides on the trap chip — to reduce the complexity.

Challenge 4: Heating. The ions' motional modes are heated by electric field noise from the trap electrodes — a phenomenon called anomalous heating. The heating rate increases as the ions get closer to the electrodes (scaling roughly as $d^{-4}$ where $d$ is the ion-electrode distance). This limits how small the trap can be made and sets a floor on the decoherence rate for motional modes.

The State of the Art (2025)

Quantinuum's H2 processor has 56 qubits with all-to-all connectivity, two-qubit gate fidelities of 99.7%, and the highest quantum volume of any quantum computer ($V_Q = 2^{20}$). The system uses a racetrack-shaped trap with multiple zones, and ions are shuttled between zones for two-qubit gates.

Part 4: The Road Ahead

What Will It Take?

A fault-tolerant quantum computer capable of running Shor's algorithm on a 2048-bit RSA key would require approximately:

• Logical qubits: $\sim 4,000$
• Physical qubits per logical qubit: $\sim 1,000$-$10,000$ (depending on physical error rate and code distance)
• Total physical qubits: $\sim 4$ million to $\sim 40$ million
• Physical error rate: $< 10^{-3}$ (below the surface code threshold)
• Gate depth: $\sim 10^{10}$ T gates (the bottleneck for Shor's algorithm)

No current technology is close to these requirements. The gap is primarily in qubit count and total gate depth, not in individual gate fidelity (which is already near the threshold for several platforms).

Hybrid and Modular Approaches

The consensus emerging in the field is that no single monolithic chip will contain millions of qubits. Instead, future quantum computers will be modular — multiple smaller processors connected by quantum links (microwave, optical, or ion shuttling). This "quantum internet on a chip" architecture distributes the engineering challenges but introduces new ones (inter-module gate fidelity, latency, bandwidth).

The Timeline Question

Estimates for when fault-tolerant quantum computing will be achieved range from the optimistic (2030-2035, from industry roadmaps) to the cautious (2040-2050 or later, from independent assessments). The honest answer is: nobody knows. The engineering challenges are formidable, and history shows that technology forecasting in quantum computing has been consistently overoptimistic.

What is certain is that the underlying quantum mechanics works — every experiment confirms the predictions of Chapters 1-37 of this textbook to extraordinary precision. The question is not whether quantum computing is possible in principle, but when and how it will be achieved in practice.

Discussion Questions

1. The DiVincenzo criteria were formulated in 2000. Are they still the right criteria? Would you add or modify any of them given what we now know about quantum error correction and fault tolerance?

2. Superconducting qubits have many more qubits but lower fidelity; trapped ions have fewer qubits but higher fidelity. Which metric matters more for near-term applications? For fault-tolerant computing?

3. The wiring bottleneck for superconducting qubits and the laser complexity for trapped ions are both engineering challenges, not physics limitations. How might advances in integrated photonics, cryogenic electronics, or MEMS technology address these challenges?

4. Google and IBM are pursuing superconducting qubits; Quantinuum and IonQ are pursuing trapped ions. Is it likely that one technology will "win," or will different technologies serve different niches?

5. The timeline for fault-tolerant quantum computing is highly uncertain. How should funding agencies, cryptographers, and industry plan in the face of this uncertainty?

Further Exploration

• Read: DiVincenzo, D. P., "The physical implementation of quantum computation," Fortschritte der Physik 48, 771-783 (2000).
• Watch: John Preskill's lectures on quantum computing hardware at Caltech (available on YouTube).
• Explore: IBM Quantum Experience (quantum-computing.ibm.com) — run circuits on real superconducting hardware.
• Read: Bruzewicz, C. D. et al., "Trapped-ion quantum computing: Progress and challenges," Applied Physics Reviews 6, 021314 (2019).