Case Study: Budgeting a Magic-State Factory

Executive Summary

In a surface-code architecture, Clifford gates are comparatively cheap and $T$ gates are not. The gap is not marginal: in a large algorithm, the machinery producing magic states typically consumes more than half the chip and sets the clock rate of the entire computation.

This case study budgets a factory for a realistic algorithm — how many $T$ gates, how many distillation rounds, how much area, how much time — and then examines the two developments that could change the picture substantially.

Skills applied

• Computing distillation output error and yield (§25.14).
• Sizing a factory against an algorithm's $T$-rate demand.
• Trading factory area against computation time.
• Evaluating $T$-count reduction as an optimization target.

Phase 1: The demand side

Target algorithm: quantum chemistry simulation requiring $10^{10}$ $T$ gates, on 200 logical qubits, with a total failure probability under 1%.

Per-$T$ error budget:

$$\varepsilon_T \le \frac{0.01}{10^{10}} = 10^{-12}$$

Every magic state consumed must have error below $10^{-12}$.

Phase 2: Distillation

Raw magic states are prepared by injection, with error roughly equal to the physical error rate — call it $10^{-3}$. Distillation improves this.

The standard 15-to-1 protocol consumes 15 states of error $\varepsilon$ and outputs 1 of error $\approx 35\varepsilon^3$:

Two rounds overshoot the $10^{-12}$ requirement substantially, and one round falls short. In practice architects use two rounds with a cheaper second stage, or intermediate protocols, but for budgeting purposes: 225 raw states per usable $T$ gate.

$$10^{10} \text{ } T \text{ gates} \times 225 = 2.25\times10^{12} \text{ raw magic states}$$

Phase 3: The area cost

Each distillation round runs inside surface-code patches. A 15-to-1 factory at distance $d$ occupies roughly $15 \times 2d^2$ physical qubits plus routing overhead — call it $\sim20d^2$.

At $d = 27$ (for $10^{-12}$ logical error at $\Lambda \approx 5$):

$$\text{One level-1 factory} \approx 20 \times 27^2 \approx 15{,}000 \text{ physical qubits}$$

A level-2 factory contains 15 level-1 factories plus its own overhead: $\approx 250{,}000$ physical qubits.

Compare the data: 200 logical qubits at $2d^2 = 1{,}458$ each is $\approx 292{,}000$ physical qubits.

$$\textbf{One} \text{ level-2 factory} \approx \textbf{86\% of the entire data register.}$$

Phase 4: The time cost — and why you need many factories

A level-2 factory produces one distilled state per cycle, where a cycle is roughly $d$ rounds of syndrome extraction at ~1 μs each: $\approx 27\,\mu s$. With pipelining, throughput is about one state per level-1 cycle after fill.

If the algorithm needs $10^{10}$ $T$ gates and one factory produces one state per ~30 μs:

$$10^{10} \times 30\,\mu s = 3\times10^{5}\,\text{s} \approx 3.5 \text{ days}$$

with a single factory — and during that time the data register mostly idles, accumulating errors while waiting.

Run 100 factories in parallel and the computation finishes in ~50 minutes, at a cost of $100 \times 250{,}000 = 2.5\times10^{7}$ physical qubits for factories alone.

The architectural reality. In any time-constrained fault-tolerant computation, the chip is a magic-state factory with a small computer attached. This is why floor plans in surface-code architecture papers show data patches as a modest island surrounded by distillation.

Phase 5: The two levers

Lever 1: reduce $T$-count. Since cost is linear in $T$-count, halving it halves everything — factory area, runtime, total qubits. This has made $T$-count optimization one of the most active areas in quantum compilation:

• Better arithmetic circuits (windowed multiplication, as in the Chapter 15 estimate).
• $T$-count-aware synthesis of rotations (Ross–Selinger reduced the cost of an arbitrary rotation from thousands of $T$ gates to ~$3\log_2(1/\delta)$).
• Circuit identities that cancel $T$ gates.
• Choosing algorithms with intrinsically low $T$-count.

Lever 2: cheaper magic states. Several directions, all active:

• Better distillation protocols with improved yield or fewer rounds.
• Magic-state cultivation, which grows high-fidelity states directly at small distance and skips a distillation level — recent work suggests order-of-magnitude savings.
• Codes with transversal $T$, e.g. 3D colour codes, trading a different overhead for eliminating distillation.

Either lever moves total cost more than a comparable improvement in qubit count, which is the strategic point.

Phase 6: Implications for algorithm design

Three consequences that ought to change how algorithms are written for fault-tolerant hardware:

1. Count $T$ gates, not total gates. A circuit with $10^6$ Cliffords and $10^3$ $T$ gates is far cheaper than one with $10^4$ Cliffords and $10^4$ $T$ gates, despite the second having 100× fewer gates.
2. Prefer Clifford-heavy formulations. Restructuring to push work into Clifford operations pays enormously.
3. Approximate rotations coarsely. Rotation synthesis costs $\sim3\log_2(1/\delta)$ $T$ gates, so demanding $\delta = 10^{-15}$ when $10^{-6}$ suffices costs 2.5× more $T$ gates for nothing — the same precision-budget principle as the QFT truncation study (Chapter 14).

Discussion Questions

1. Factories consume 46–99% of the chip depending on parallelism. Explain the trade and how you would choose a point on it.
2. Two distillation rounds overshoot $10^{-12}$ while one falls short. What does that suggest about protocol design?
3. Halving $T$-count halves total cost. Compare that against halving the physical error rate — which is easier to achieve?
4. Magic-state cultivation could skip a distillation level. Estimate the saving from the table in Phase 4.

Your Turn: Extensions

• Compute distilled error for three rounds and find the smallest raw error for which one round suffices at $10^{-12}$.
• Size a factory for an algorithm with $10^{8}$ $T$ gates and compare against the $10^{10}$ case.
• Estimate the $T$-count of a modular exponentiation circuit and cost its factory requirements.
• Read a magic-state cultivation paper and recompute Phase 4 with its numbers.

Key Takeaways

• Reaching $10^{-12}$ magic-state error takes two rounds of 15-to-1 distillation, consuming 225 raw states per usable $T$ gate.
• A single level-2 factory rivals the entire data register in size; parallel factories push the chip to 90–99% distillation.
• Runtime is set by magic-state throughput, so the factory count is a direct area-versus-time trade.
• $T$-count is the dominant cost driver: halving it halves area, runtime, and total qubits.
• Design fault-tolerant algorithms to minimize $T$ gates and to demand no more rotation precision than the error budget requires.