Case Study 2: Should This Circuit Be Dynamic?

"The technique works. That is not the same as the technique being worth it, and the difference is a measurement."

Executive Summary

Dynamic circuits are supported, they are interesting, and they are a legitimate research direction. None of that answers the question a working engineer actually has: for my circuit, on my device, today — should I use one?

This case study answers it for three concrete cases, and the answers differ. One is a clear yes, one is a clear no, and one is genuinely marginal in a way that is worth understanding. The method generalizes, and it is the same method as Chapter 8's Case Study 2: measure the knobs rather than reasoning about them.

Skills applied: qubit reuse (§9.5); dynamic-circuit cost (§9.7); the latency argument (§9.7); ansatz cost measurement (Ch. 8 §8.8).

The Decision Framework

Four questions, in order. The first "no" ends the analysis.

  1. Does the circuit have qubits that genuinely finish early? If every qubit stays entangled to the end, there is nothing to reuse and the answer is no.
  2. Is width actually the binding constraint? If the device has spare qubits, converting width to depth is a pure loss.
  3. Does the added depth fit inside the coherence budget? Reset is a measurement plus a conditional gate, and measurement is the slowest operation on the device.
  4. Can you tolerate the latency? The measure-decide-act round trip is hundreds to thousands of nanoseconds, during which every other qubit sits idle — and it appears in no gate count.

Case A: A VQE Ansatz — Clear No

The project's own circuit, and the one this book's checkpoint settles.

Question 1 fails immediately. A hardware-efficient ansatz alternates rotation layers with entangling layers, and the entangling layers exist precisely to keep every qubit correlated with every other. At no point does a qubit finish.

Measured anyway, because a measurement beats an argument:

  variant     ISA depth    2q   measure   reset
  ----------------------------------------------
  static             24     6         4       0
  dynamic            29     6         2       1

  depth ratio: 1.21x

21% more depth, the same two-qubit gate count, and no qubits saved — the dynamic variant reused one ancilla to measure two Pauli terms sequentially instead of measuring them in separate circuits. The circuit got worse on every axis that matters and better on none.

Verdict: no, and the value of running the measurement is that the conclusion is now data. When someone proposes this in six months — and someone will, because mid-circuit measurement is genuinely interesting — the answer is a table rather than an opinion.

Case B: A Sequential Sampling Circuit — Clear Yes

Now a circuit with the opposite structure: draw $k$ independent samples, each requiring one qubit, with no correlation between them.

qc = QuantumCircuit(1, k)
for i in range(k):
    qc.h(0)
    qc.measure(0, i)
    if i < k - 1:
        qc.reset(0)

Measured, one physical qubit producing $k$ independent flips:

  2 flips on ONE qubit: 4 outcomes (expect 4), worst deviation from uniform 0.0029
  3 flips on ONE qubit: 8 outcomes (expect 8), worst deviation from uniform 0.0048
  4 flips on ONE qubit: 16 outcomes (expect 16), worst deviation from uniform 0.0068

Question 1 passes emphatically — each qubit finishes the moment it is measured. Question 2 depends on your device, and if you need 20 samples on a 5-qubit machine it passes decisively. Question 3 is the real constraint.

It is tempting to read a trend into the third column — 0.0029 → 0.0048 → 0.0068, rising with each reuse — and conclude that each reset inherits the readout error of the measurement it is built on. An earlier draft of this case study did exactly that and printed the conclusion "reuse degrades, cumulatively." It is wrong twice over, and the correction is worth more than the claim was.

📊 What the Numbers Say

Those three numbers came off AerSimulator() with no noise model attached. There is no readout error in that simulator to inherit, so whatever the rising column is, that cannot be its mechanism.

And the column is not rising. Each figure is one draw of a shot-noise statistic at a fixed seed. Re-running each row 200 times with no seed, 8,192 shots each:

```text k flips published mean of 200 SEM sd binomial sd 2 0.0029 0.00657 0.00021 0.00292 0.00478 3 0.0048 0.00642 0.00013 0.00186 0.00365 4 0.0068 0.00558 0.00009 0.00126 0.00267 5 -- 0.00449 0.00006 0.00087 0.00192 6 -- 0.00349 0.00004 0.00058 0.00137 8 -- 0.00214 0.00002 0.00030 0.00069

mean(k=2) - mean(k=3) = +0.00015 z = +0.61 indistinguishable mean(k=3) - mean(k=4) = +0.00084 z = +5.27 FALLING mean(k=2) - mean(k=8) = +0.00443 z = +21.34 FALLING ```

The mean is flat from 2 to 3 and falls from there on, by a factor of three at eight flips. The published direction is not merely unsupported; it is backwards. Seed 1234 drew near the bottom of the $k=2$ distribution — 0.0029, against a mean of 0.00657 and a per-draw sd of 0.00292 — and near the top of the $k=4$ one. The "trend" is the gap between those two accidents.

The falling column has a cause, and it is arithmetic rather than physics. The statistic is the largest deviation of any bin from $2^{-k}$, and each bin's frequency has standard deviation $\sqrt{p(1-p)/N}$ with $p = 2^{-k}$. That shrinks as $2^{-k/2}$. Doubling the bin count gives the maximum more bins to be large in, but shrinks each bin's spread faster — so the measured maximum falls, tracking the binomial column beside it. The statistic was never measuring reuse damage. It was measuring its own bin count.

So the noiseless answer to question 3 is that reuse costs nothing at all, which is exactly what a noiseless simulator has to say. The real ceiling is physical and lives in three places this experiment cannot reach: readout error on the measurement (§9.5), reset infidelity on the qubit handed back to the pool, and the $T_2$ budget of a circuit that is now $k$ times longer (Ch. 31 §31.2). Measuring reuse damage requires a noise model or hardware — and the deviation-from-uniform statistic is the wrong instrument for it in either case.

Verdict: yes, with a ceiling — but the ceiling has to be measured where it lives. Reuse until the accumulated reset and readout error exceed what you can tolerate, on a backend that has some.

Case C: Teleportation Inside a Larger Circuit — Marginal

The interesting case. Suppose you need to move a state across a device whose connectivity does not directly link the source and destination qubits. Two options:

Static: route with SWAPs. Chapter 4 §4.6 priced this at three CNOTs per SWAP, and a route of length $\ell$ costs $3\ell$ two-qubit gates.

Dynamic: teleport. One Bell pair, one Bell measurement, two conditional corrections.

Measured, teleporting across three qubits versus the equivalent static circuit:

  circuit          ISA depth   2q
  --------------------------------
  static GHZ               9    2
  teleportation           14    2

Same two-qubit count, 56% more depth. On this comparison, static wins.

But the comparison is not fair for long routes, and that is the point of the case. The static cost grows as $3\ell$ in two-qubit gates; teleportation's cost is constant in the distance, provided the Bell pair can be distributed. So there is a crossover, and where it sits depends on the device's topology and on the latency of the conditional block.

Verdict: it depends, and the dependence is on numbers you can measure. For the short hops typical of current devices, static routing wins. For a modular architecture with slow links between chips — which is where the industry is heading — teleportation-based routing becomes the right answer, which is exactly why it is an active engineering topic rather than a curiosity.

💰 Cost and Queue — The number nobody quotes.

Every comparison above used ISA depth, and every one of them understates the dynamic circuit's cost, because the measure-decide-act latency appears in no gate count and no depth number.

Rough shapes on superconducting hardware: a single-qubit gate is tens of nanoseconds, a two-qubit gate is hundreds, a measurement is around a microsecond, and the classical round trip from measurement result to conditional pulse is hundreds of nanoseconds to microseconds.

So one conditional block can idle your other qubits for longer than a dozen gates take to execute. Against a $T_2$ of ~100 μs, a handful of conditional blocks is a meaningful fraction of your coherence budget.

When you see a dynamic-circuit result reported without its latency cost, the comparison is incomplete. Ask for the duration, not the depth — and note that Chapter 31 §31.3's scheduling tools are how you get it.

The General Method

  1. Does any qubit finish early?          no  -> stop, use static
  2. Is width the binding constraint?      no  -> stop, use static
  3. Does the added depth fit T2?          no  -> stop, use static
  4. Can you tolerate the latency?         no  -> stop, use static
                                           yes -> measure both and compare

And the measurement, always both variants, always on the target device:

for label, circuit in (("static", static_version), ("dynamic", dynamic_version)):
    isa = pm.run(circuit)
    ops = dict(isa.count_ops())
    print(label, isa.depth(),
          sum(v for k, v in ops.items() if k in ("ecr", "cz", "cx")),
          ops.get("measure", 0), ops.get("reset", 0))

🔬 Honest Assessment — Why dynamic circuits are used less than they are discussed.

They work. Hardware supports them. They are the foundation of error correction, which is the field's central goal. And they are used sparingly in practice, for a reason worth stating plainly:

On current hardware, the latency of the classical round trip is comparable to the coherence time divided by a modest number. That means a circuit with many conditional blocks spends a large fraction of its coherence budget waiting for classical decisions. Error correction needs this anyway and pays the price because there is no alternative; most other applications have an alternative and take it.

This will change. Reducing that latency is a major hardware engineering target precisely because everything fault-tolerant depends on it, and the trend is favorable.

The honest current guidance: learn dynamic circuits because they are how error correction works and because they will matter more each year — and default to static circuits for everything you run today, unless a measurement says otherwise.

Lessons

  1. "The technique works" is not "the technique is worth it." Measure both variants.
  2. Question 1 decides most cases: if no qubit finishes early, there is nothing to reuse.
  3. A VQE ansatz never passes question 1 — that is what entangling layers are for.
  4. A trend across three points at one seed is not a trend. This case study published 0.0029 → 0.0048 → 0.0068 as evidence that reuse degrades cumulatively. Two hundred repeats per row give 0.00657 → 0.00642 → 0.00558, falling to 0.00214 by eight flips — the opposite direction — and the runs were noiseless, so the proposed mechanism was impossible as well. Reuse does have a ceiling; it is readout and reset error on real hardware, and this experiment could not have seen it.
  5. Teleportation's routing cost is constant in distance; SWAP routing is linear. There is a crossover, and it moves as architectures become modular.
  6. ISA depth understates dynamic-circuit cost. Ask for duration, not depth.
  7. Record negative results. The value of Case A is that the next proposal gets a table instead of an argument.

Questions

  1. Run the four-question framework on a circuit of your own. Where does it stop?

  2. Reproduce Case B's degradation trend out to 8 reuses. Fit the deviation against the reuse count — is it linear? What does that predict for the maximum useful number of reuses at a 1% tolerance?

  3. Case C claims a crossover between SWAP routing and teleportation. Estimate where it is: at what route length $\ell$ does $3\ell$ two-qubit gates exceed teleportation's fixed cost, ignoring latency? Now include a latency of 1 μs per conditional block and redo it against a $T_2$ of 100 μs.

  4. Construct a circuit that passes questions 1 and 2 but fails question 3. What does it look like?

  5. The framework's step 4 asks whether you can tolerate the latency, without saying how to find out. Design a measurement that would tell you — using only circuits you can run. (Hint: what happens to an idle qubit's state over a known duration?)

  6. Case A's negative result was recorded as a table. Write the two-sentence note you would leave in a project's documentation so that the next person does not re-derive it, and say what would make you revisit it.

  7. Hardest. Error correction requires dynamic circuits and pays the latency cost because there is no alternative. Estimate the constraint: for a surface-code cycle that must complete within the qubits' coherence time, and given a classical round-trip latency $\tau$, how small must $\tau$ be relative to $T_2$? Look up a current figure for both and say how far away we are. (Chapter 25 §25.8 has the code-cycle side of this.)