Quiz: Hardware-Aware Programming

Answers with explanations at the end.

1. State this chapter's thesis in one sentence.

2. FakeSherbrooke has 127 qubits. How many edges does it have, how many would a complete graph have, and what is the maximum degree?

3. Why is the heavy-hex lattice's low connectivity deliberate rather than a limitation?

4. Define routing overhead and say what a value of 1.0 means.

5. Give the routing overhead for full, circular, and linear entanglement on a 6-qubit EfficientSU2.

6. circular is linear plus one edge per repetition. What did those edges cost?

7. Complete the sentence: "Routing overhead is a property of __, not of ____." Justify it.

8. Hardware-aware at level 1 scored 0.9116; naive at level 3 scored 0.7720. What does this demonstrate?

9. Isolate the two variables: what is circuit shape worth at a fixed optimization level, and what is optimization level worth at a fixed shape?

10. On the linear ansatz, level 3 is deeper than level 1 and scores better. Chapter 28 found the opposite on another circuit. Are both correct?

11. A hand-picked connected chain produced a shallower circuit and scored 0.6790 against the automatic layout's 0.9116. What went wrong?

12. State the difference between what the coupling map tells you and what the calibration record tells you.

13. After fixing the mistake and choosing by measured error, the hand-picked chain scored survival 0.9764 against the transpiler's 0.9587 — and still lost the fidelity measurement. Why?

14. Give the rule this chapter's two layout experiments establish.

15. When should you set initial_layout?

16. coupling_map.neighbors(q) has a trap. What is it, and what did it produce?

17. Name three ways to design a circuit for the interaction graph rather than against it.

18. Linear entanglement is less expressive than all-to-all. How should that trade be decided?

19. Why do Chapters 16 and 24 point the same way as this chapter on ansatz choice?

20. The hardware-aware circuit reached 0.9310. Chapter 28's optimized circuit reached 0.129. What explains the difference, and what does it not mean?

Answers

1. The cheapest optimization is not needing one — matching your circuit's interaction graph to the chip's is worth more than any amount of transpiler effort applied afterwards.

2. 144 undirected edges; a complete graph would have 8,001; maximum degree 3, with most qubits having exactly two neighbours.

3. Because fewer neighbours means less crosstalk, and crosstalk is much harder to correct than routing. The lattice trades a problem the compiler can solve for one it cannot.

4. Hardware two-qubit gates divided by logical ones. 1.0 means the interaction graph embeds in the chip and routing was free — a graph embedding rather than a routing problem.

5. full 3.3× (45 → 147), circular 3.8× (18 → 69), linear 1.0× (15 → 15).

6. 54 hardware gates instead of 15 — the ring-closing edge is not on the chip. One edge you did not need cost more than the fifteen you did.

7. "Routing overhead is a property of your circuit, not of the transpiler." The transpiler realizes the interaction graph you asked for on the graph the chip provides; if they match the job is free, and if they do not, optimization only finds a cheaper route through the same mismatch.

8. That circuit shape dominates optimization level — a hardware-aware circuit at the lowest useful optimization level beat a naive one at the highest, by +0.1397. No optimization level rescues the wrong shape.

9. Shape at a fixed level: +0.1658 (naive L1 → aware L1). Level at a fixed shape: +0.0262 (naive L1 → naive L3). Shape is worth six times the optimization level.

10. Yes. Depth and two-qubit count are different proxies governing different physics (decoherence versus gate error), and which one dominates depends on the circuit. Which proxy wins is circuit-specific, which is the argument for measuring rather than reasoning.

11. Two of its five edges have error rate 1.0000 — dead links, uncalibrated or failed. The chain was a valid path in the coupling map and its predicted survival was exactly zero. Every structural metric improved and the outcome collapsed.

12. The coupling map says which qubits can interact. The calibration record says which pairs work. Different questions, different data — and a graph search over the coupling map alone will route through broken hardware without complaint.

13. Because the survival product — two-qubit gate errors along the path — is an incomplete model. It ignores readout error, $T_1$/$T_2$ on the specific qubits, single-qubit gate errors, and the scheduling that follows layout selection. VF2Layout scores candidate embeddings against the full error model in the backend Target.

14. Choose the shape; leave the layout. Shape is where your knowledge is irreplaceable — you know your interaction graph, and the transpiler can only accept it. Layout is where the transpiler's knowledge is irreplaceable. Shape was worth +0.1658; hand-picking layout cost −0.0157 done carefully and −0.2326 done by graph structure alone.

15. Only for information the transpiler cannot have: a qubit you know is recalibrating that the Target has not caught up with, a region reserved for another job on a shared device, an exact reproduction of an earlier run, or an experiment where qubit identity is the variable. Not as a general-purpose optimization.

16. It returns only successors — the coupling map is directed. Using it as an undirected adjacency made 29 qubits appear to have zero neighbours and produced a wrong degree distribution while drafting §29.1.

17. Any three of: prefer linear or grid entanglement in variational ansätze; do not close rings you do not need; reorder your problem to match the chip (for QAOA the interaction graph is fixed, but the vertex-to-qubit assignment is not); use the chip's native gates (ecr, cz, MS/GPi); use mid-circuit measurement and qubit reuse to convert width into depth.

18. Empirically, on a simulator, noiselessly — run the optimization with both ansätze and see whether the cheaper one reaches the answer at all. If it does, expressibility is not the binding constraint and fidelity decides. For Chapter 24's H₂ a four-parameter problem-informed ansatz reached the exact ground state to $8.88\times10^{-16}$; the shot budget bound, not expressibility.

19. Because Chapter 16 §16.6 found problem-informed ansätze are the main defence against barren plateaus, and Chapter 24 §24.4 noted QAOA gets a problem-informed structure for free. Both favour structured, non-generic entanglement patterns — the same ones that route cheaply. The ansatz that runs is often also the ansatz that trains.

20. The hardware-aware circuit is 6 qubits with 15 two-qubit gates; Chapter 28's had 257. Hardware-aware design did not make noise stop mattering — it made the circuit small enough that noise matters less. It does not mean the noise problem is solved; Chapter 25's threshold is still the binding constraint at any interesting scale.