Chapter 29: Hardware-Aware Programming

Chapter 28 measured what optimization can do: level 0 to level 1 roughly doubles the surviving signal, and everything above that is refinement. It also measured what optimization cannot do — the best setting still returned 12.9% of the noiseless answer.

This chapter is about the other lever. The cheapest optimization is not needing one.

The headline measurement: an ansatz whose entangling pattern matches the chip, transpiled at level 1, beats a naive all-to-all ansatz transpiled at level 3 by $+0.1397$ in output fidelity. No optimization level rescues the wrong circuit shape.

And then a correction to the obvious conclusion. "Hardware-aware" sounds like it means choosing your own qubits, and §29.4 measures what happens when you do: a hand-picked layout that scored perfectly on connectivity produced 0.6790 against the transpiler's automatic 0.9116. Even after fixing the mistake and picking with calibration data, the hand layout still lost.

Choose the circuit shape yourself. Leave the layout to the transpiler.

29.1 The chip is not a complete graph

Everything in Parts I through IV was written as though any qubit could interact with any other. No hardware works that way.

FakeSherbrooke, a snapshot of a real 127-qubit device:

   127 qubits, 144 undirected edges
   degree distribution: {1: 2, 2: 89, 3: 36}

Maximum degree three. Most qubits have exactly two neighbours. This is the heavy-hex lattice — chosen deliberately, because lower connectivity means less crosstalk, and crosstalk is harder to fix than routing.

A complete graph on 127 qubits would have 8,001 edges. This chip has 144. Every two-qubit gate your algorithm wants between non-adjacent qubits must be routed — realized as a chain of SWAPs, each costing three two-qubit gates on this basis.

Chapter 17 measured that overhead at up to 3.18×. This chapter measures what you can do about it before the transpiler ever sees your circuit.

Why the chip has only three neighbours per qubit

Low connectivity reads as a limitation until you ask what the alternative costs. On superconducting hardware every coupler you add brings three problems with it, and only one of them has a software fix.

Crosstalk. Two capacitively coupled qubits are never fully independent. Driving one shifts the other's transition frequency slightly, so a pulse aimed at qubit $a$ leaves a small unwanted rotation on everything $a$ touches. The effect accumulates with the number of attached couplers: a degree-5 qubit collects crosstalk from five directions instead of two. And crosstalk is a correlated error — Chapter 13's mitigation techniques and Chapter 25's error-correction thresholds both assume errors that are, to a good approximation, independent. Correlated noise is the assumption-breaking kind.

Frequency collisions. Each qubit needs a transition frequency far enough from its neighbours' that a pulse meant for one does not drive another, and far enough from the sums and differences that arise between coupled pairs. Those constraints are pairwise, so the closed neighbourhood of a degree-$d$ qubit contains $\binom{d+1}{2}$ pairs that must all be kept out of resonance simultaneously:

$$d = 2 \;\Rightarrow\; 3 \text{ pairs} \qquad d = 3 \;\Rightarrow\; 6 \qquad d = 5 \;\Rightarrow\; 15$$

Real collision conditions are more numerous than the pairwise ones, so this is a floor rather than a count — but the scaling is the point. Doubling the degree roughly triples the number of frequency constraints a fabricated chip has to satisfy at once, and a chip that misses one has a region that does not work.

Yield. More couplers means more Josephson junctions, more chances for one to land off-target, and more of the chip taken out by each miss. That is not hypothetical here. Nine of this chip's 144 edges carry a two-qubit error of exactly 1.0000 — they are dead, and §29.4 is about what happens when your circuit lands on one.

The trade is therefore explicit and deliberate: less crosstalk and better yield, in exchange for more routing. Routing is a compiler problem, and compilers get better. Crosstalk and collisions are physics, and they do not.

The distances the lattice actually imposes

"Maximum degree three" is a local statement. The global consequence is what routing has to pay:

   undirected edges                              144
   sum of all degrees   (2 x 89 + 3 x 36 + 1 x 2) 288 = 2 x 144
   mean degree                                2.2677
   graph diameter                                 26
   mean shortest-path distance between two qubits  11.1324
   pairs at distance 1                    144 / 8,001 = 1.80%

Two qubits picked at random on this chip are eleven hops apart, and the two furthest are twenty-six. Only 1.8% of qubit pairs can interact directly at all. A circuit written as though the hardware were a complete graph is not asking for a slightly harder version of what the chip does; it is asking for something 98.2% of which does not exist and has to be manufactured out of SWAPs.

📐 Math Aside: what 144 edges on 127 qubits forces.

The handshake lemma — the sum of all degrees equals twice the number of edges — turns the degree distribution into an arithmetic check on the edge count:

$$2|E| = \sum_v \deg(v) = 1\cdot 2 + 2\cdot 89 + 3\cdot 36 = 2 + 178 + 108 = 288 \;\Rightarrow\; |E| = 144$$

The two distributions in §29.1 are therefore not independent facts; either one implies the other, and if they disagree you have a bug rather than a discovery. (This is worth knowing because they did disagree while this section was being drafted — see the debug note below.)

The mean degree $2|E|/|V| = 288/127 = 2.27$ also bounds how fast a neighbourhood can grow. From any qubit you reach at most 3 others in one hop, and at most 2 new ones per hop after that, so the ball of radius $r$ holds at most $3 \cdot 2^{r} - 2$ qubits. Covering 127 needs $2^{r} \ge 43$, so $r \ge 6$: no degree-3 graph on 127 vertices can have a diameter below 6. This one has 26, because heavy-hex is far sparser than the bound allows — the hexagonal holes cost distance.

The practical form: the routing cost of a two-qubit gate between qubits at distance $d$ is $3(d-1)$ extra two-qubit gates, because bringing them together takes $d-1$ SWAPs and each SWAP decomposes into three. At the mean distance of 11.13, that is 30 extra gates for one gate you asked for.

🐛 Debug This: coupling_map.neighbors() is directed, and it will lie to you quietly.

The first draft of the degree distribution above was wrong, and wrong in a way that produced a plausible-looking table rather than an exception:

text coupling_map.neighbors(q), used directly: {0: 29, 1: 54, 2: 42, 3: 2} both directions unioned: {1: 2, 2: 89, 3: 36}

Twenty-nine qubits appeared to have no neighbours at all, and only two appeared to have three. CouplingMap stores directed edges — neighbors(q) returns successors — and a qubit that happens to be the target of every coupler it touches returns an empty set.

The tell was arithmetic, not intuition: summing the wrong distribution gives $0\cdot 29 + 1\cdot 54 + 2\cdot 42 + 3\cdot 2 = 144$, exactly the directed edge count, when the handshake lemma says the degree sum must be $2|E| = 288$. A degree sum that equals $|E|$ rather than $2|E|$ is the signature of this bug.

The fix is one of:

```python adj = {} for a, b in backend.coupling_map: # iterate edges, union both ways adj.setdefault(a, set()).add(b) adj.setdefault(b, set()).add(a)

backend.coupling_map.graph.neighbors_undirected(q) # or ask rustworkx ```

And note what the bug would have done downstream if it had gone unnoticed: a chain search over this adjacency would have refused to route through 29 perfectly good qubits, and any layout selector built on it would have quietly restricted itself to a fraction of the chip.

29.2 The same ansatz, three shapes

EfficientSU2 on 6 qubits, 3 repetitions, differing only in which pairs get entangled:

   entanglement                  logical 2q   L1 ecr   L3 ecr   L3 depth
   full (all-to-all)                     45      147      116        347
   circular                              18       69       54        206
   linear (matches a chain)              15       15       15         53

Read the linear row twice. 15 logical two-qubit gates become 15 hardware gates. Zero routing overhead.

Now the full row. 45 logical gates become 147 at level 1 — a 3.3× blow-up — and level 3 grinds it down to 116, still 2.6×. Those extra 71–102 gates are pure routing: SWAPs inserted to bring qubits together that the chip keeps apart.

⚛️ The Physics Underneath: routing overhead is a property of your circuit, not of the transpiler.

The transpiler's job is to realize the interaction graph you asked for on the interaction graph the chip provides. If those graphs match, the job is free. If they do not, the cost is set by how badly they mismatch, and no amount of optimization effort changes that — it only finds a cheaper route through the same mismatch.

A linear entanglement pattern on a chip containing linear chains is a graph embedding, not a routing problem.

The circular pattern is instructive as a middle case: 18 logical gates become 54. The one extra edge closing the ring — connecting the last qubit back to the first — is not present on the chip, and paying for it costs 36 gates.

One edge you did not need cost you more than the fifteen you did.

Where the three logical counts come from

The left column of that table is not measured, it is counted. EfficientSU2(n, reps=r) applies one entangling layer per repetition, and the three patterns differ only in how many pairs that layer touches:

   pattern     pairs per layer      r = 3, n = 6      measured
   linear             n - 1                    15           15
   circular           n                        18           18
   full          n(n-1)/2                      45           45

So the logical ratio between the extremes is fixed by arithmetic:

$$\frac{\text{full}}{\text{linear}} = \frac{n(n-1)/2}{n-1} = \frac{n}{2} = 3 \quad\text{at } n = 6$$

But the hardware ratio is $147/15 = 9.8$. The logical gap of 3× arrives at the device as a gap of nearly ten, because the two patterns are not charged the same rate: linear pays 1.0× and full pays 3.27×, and $3 \times 3.27 = 9.8$.

That factorization is the useful part. A shape decision has two multiplicative effects — how many gates you ask for, and what each one costs to place — and the second is invisible in the source code. Since $n/2$ grows with the qubit count and the routing overhead has no reason to shrink, this predicts the gap widens as circuits get wider. Exercise 29.10 asks you to measure it at 4, 6, 8 and 10.

📐 Math Aside: the SWAP bill, derived, and how close the naive model gets.

Put the six logical qubits on a physical chain so that logical $i$ sits on the $i$-th link. A gate between logical $i$ and $j$ then spans distance $d = |i - j|$, needs $d-1$ SWAPs to bring the pair together, and each SWAP is three two-qubit gates. The naive cost of one entangling gate is therefore

$$C(d) = 3(d-1) + 1$$

The ring-closing edge. On a 6-chain, logical qubit 5 and logical qubit 0 are at opposite ends: $d = 5$, so $C(5) = 3 \cdot 4 + 1 = 13$. With three repetitions the ring costs $3 \times 13 = 39$ gates on top of linear's 15:

text predicted: 15 + 39 = 54 measured (level 3, circular): 54

Exactly. Which is a better agreement than the model deserves — it assumes each wrap-around starts from the same qubit ordering, and in reality the first one permutes the chain before the second one runs. At level 1 the same circuit costs 69, so the model matches one of the two measurements and misses the other by 28%. Treat it as an order-of-magnitude estimator that happened to land, not as a validated formula.

All-to-all, with no SWAP reuse. Sum $C(d)$ over all 15 pairs on a 6-chain, where distance $d$ occurs $6-d$ times:

$$\sum_{i

Three layers gives 225. The measured counts are 147 at level 1 and 116 at level 3 — 65% and 52% of the no-reuse bound. The transpiler is not merely inserting SWAPs; it is reusing them, letting one SWAP serve several later gates, and that recovers roughly a third to a half of the naive bill.

This is the honest version of "the transpiler cannot fix your shape." It cannot, but it is working hard inside the shape you gave it, and the 102 routing gates in the level-1 full circuit are already the cheap answer to a badly posed question.

The ring is not a rounding error: this chip has no six-cycle

The circular row deserves a stronger explanation than "one more edge." Measure the girth — the length of the shortest cycle anywhere in the coupling graph:

   FakeSherbrooke girth = 12

The shortest closed loop on this chip is twelve qubits long. There is no 6-cycle anywhere, on any choice of qubits, at any layout. entanglement="circular" on six qubits is therefore not an embedding that the transpiler failed to find — it is an embedding that does not exist, and the SWAPs are mandatory rather than merely likely.

The same argument disposes of the full row without running anything. All-to-all entanglement on $n$ qubits is the complete graph $K_n$, in which every vertex has degree $n-1$. On six qubits that is degree 5, and this chip's maximum degree is 3, so $K_6$ cannot be a subgraph of it — nor of any heavy-hex device of any size. Routing is forced by the degree sequence alone.

So the three rows of §29.2's table are three different answers to a question that graph theory settles before the compiler starts:

   linear    P6  = a path        embeds (chains exist)          overhead 1.0
   circular  C6  = a 6-cycle     CANNOT embed (girth is 12)     overhead 3.8
   full      K6                  CANNOT embed (needs degree 5)  overhead 3.3

And it makes a prediction worth testing: a ring becomes free at twelve qubits, not at six, because twelve is the first cycle length the lattice actually contains. If your algorithm genuinely needs periodic boundary conditions, the width at which you can have them for free is a property of the chip.

⚙️ Under the Transpiler: what SABRE is doing with those 102 gates.

Qiskit's default routing pass is SABRE — SWAP-based bidirectional heuristic search. It does not solve the routing problem; the problem is NP-hard, and 147 against a no-reuse bound of 225 is what a good heuristic looks like.

The loop, roughly: take the front layer of gates that are not yet executable, score every SWAP adjacent to those qubits by how much it reduces the summed distance of the front layer — with a lookahead term over the next few layers and a decay term discouraging repeated use of the same qubits — apply the best one, and repeat. Then reverse the circuit and route it backwards, and use the mapping that falls out as a better initial layout for the next forward pass. That bidirectional refinement is where the "co-design layout with routing" behaviour in Chapter 10 §10.6 comes from, and it is why SABRE beat trivial and dense layout there, 28 gates against 34.

Two consequences you can see in this chapter's numbers:

• It reuses SWAPs. A SWAP inserted for one gate leaves the qubits somewhere useful for the next, which is the whole gap between 225 and 147.
• It is randomized. Ch. 10 measured six seeds producing two-qubit counts from 18 to 21 on one circuit. §29.5 measures what that randomness does to this chapter's two shapes, and the answer is not the same for both.

What SABRE cannot do is invent an edge. If you hand it $K_6$ on a degree-3 lattice, every one of its choices is a choice about which SWAPs to pay for, never whether to pay.

🔀 In Another Framework: connectivity is modelled in three different places.

Cirq (1.7.0) puts the topology in the qubit type. A cirq.LineQubit knows it lies on a line and a cirq.GridQubit knows its coordinates, so writing an all-to-all circuit on a grid device is something you have to do on purpose rather than by default. Routing is cirq.RouteCQC, basis translation is cirq.optimize_for_target_gateset, and the two are separate transformers you compose. The design pushes §29.2's decision earlier — into how you name your qubits.

PennyLane (0.45.1) treats routing as a transform: qml.transforms.transpile(tape, coupling_map, device=None). The coupling map is an explicit argument rather than a property of a backend object, which makes it easy to ask "what would this ansatz cost on a different topology?" — exactly Exercise 29.32's question.

Q# (Chapter 15) has no coupling map in the programming model at all. You write against an abstract machine, and the resource estimator prices a connectivity assumption rather than a specific chip. That is the right abstraction for the fault-tolerant regime Chapter 15 targets, where the physical layout is hidden underneath the error-correcting code — and the wrong one for deciding which entanglement string to pass today.

The measurement is architecture-specific, the method is not. Count logical two-qubit gates, count hardware two-qubit gates, divide.

29.3 The measurement that settles it

Structural counts are proxies, and Chapter 28 §28.3 measured them disagreeing with outcomes. So run all of it on a noise model built from the device, five transpiler seeds, 20,000 shots each, scoring $1 - \text{TVD}$ against the noiseless distribution:

   configuration                                        ecr  depth   1-TVD     std
   full entanglement,   level 1, auto layout            147    396  0.7458  0.0057
   full entanglement,   level 3, auto layout            118    334  0.7720  0.0054
   linear entanglement, level 1, auto layout             15     41  0.9116  0.0028
   linear entanglement, level 3, auto layout             15     54  0.9310  0.0051

Hardware-aware at level 1 (0.9116) beats naive at level 3 (0.7720) by $+0.1397$ — more than twenty standard errors, and roughly five times the gap between level 1 and level 3 on either shape.

(These are stochastic measurements with a standard deviation around 0.005, so the last digit moves between runs. The gaps are what matter, and they are far larger than the scatter.)

What a perfect device would have scored

Before reading 0.9310 as "7% of the signal lost," find out what the scoring procedure itself costs. Run the noiseless simulator at the same 20,000 shots and score it against the same 200,000-shot reference:

   ansatz      support   noiseless 1-TVD (5 seeds)     std
   linear           64                     0.9793   0.0020
   circular         64                     0.9803   0.0020
   full             64                     0.9793   0.0019

A device with no noise at all scores 0.9793, not 1.0000. The missing 0.0207 is sampling, not physics: 20,000 shots spread over 64 outcomes cannot reproduce a distribution more precisely than that.

That changes how the table reads in two ways, and they point in opposite directions.

Absolute scores are biased low, so the good result is better than it looks. The linear ansatz at level 3 gives up $0.9793 - 0.9310 = 0.0483$ to the device, not $0.0690$. It is recovering 95% of everything the measurement was capable of showing.

But every row carries the same bias, so it cancels in every comparison. The $+0.1397$ headline is a difference of two scores measured the same way against the same reference, and subtracting 0.0207 from both changes nothing. The gaps are clean; only the absolute numbers need the correction.

Deficits from the ceiling make the shape effect much starker than the raw scores do:

   configuration                       1-TVD    deficit from 0.9793   ratio to linear L1
   linear entanglement,   level 1     0.9116                 0.0677                1.00
   linear entanglement,   level 3     0.9310                 0.0483                0.71
   full entanglement,     level 1     0.7458                 0.2335                3.45
   full entanglement,     level 3     0.7720                 0.2073                3.06

The naive circuit at level 3 carries three times the noise burden of the hardware-aware circuit at level 1, on the same device, in the same run.

Note also that the burden ratio (3.1×) is well below the two-qubit gate ratio ($118/15 = 7.9\times$). Total variation distance is bounded above by 1, so it compresses large differences: a distribution that has decohered most of the way to uniform cannot get much further away, and the metric stops resolving. That is a reason to prefer $1-\text{TVD}$ for comparing circuits that mostly work, and to distrust it for ranking circuits that mostly do not.

📐 Math Aside: how many standard errors is $+0.1397$?

Each row is the mean of five transpiler seeds, so the standard error of the mean is $\sigma/\sqrt{5} = \sigma/2.236$, and the standard error of a difference of two independent means adds in quadrature:

text comparison sigma_a sigma_b SE(diff) gap gap/SE aware L1 vs naive L3 (shape+level) 0.0028 0.0054 0.00272 0.1397 51.4 naive L1 vs naive L3 (level only) 0.0057 0.0054 0.00351 0.0262 7.5 aware L1 vs aware L3 (level only) 0.0028 0.0051 0.00260 0.0194 7.5

The chapter says "more than twenty standard errors" for the headline gap, which is the conservative reading: it uses the per-seed scatter $\sqrt{\sigma_a^2 + \sigma_b^2} = 0.0061$ as the unit rather than the standard error of the mean, giving $0.1397/0.0061 = 22.9$. Both readings support the same conclusion, and quoting the smaller one is the right habit — Chapter 27 §27.5's whole subject is what happens when you quote the flattering statistic and it turns out to be a small sample.

The two level effects are the interesting ones. Both come out at 7.5 standard errors — so optimization level is not doing nothing, and this chapter is not claiming it does. It is doing something real, reproducible, and roughly one-sixth the size of the shape effect. Chapter 28 §28.3 found level 2 versus level 3 not significant at $+0.0028 \pm 0.0065$; level 1 versus level 3 is a different and larger comparison, and it survives.

🔬 Honest Assessment: circuit shape dominates optimization level.

Isolating the two variables and comparing like for like:

text optimization level, shape held fixed (naive L1 -> naive L3): +0.0262 circuit shape, level held fixed (naive L1 -> aware L1): +0.1658 both together (naive L1 -> aware L3): +0.1867

Shape is worth six times the optimization level, at a fixed level. Chapter 28's entire optimization stage — three levels, a dozen passes, a convergence loop — moved this circuit by $+0.0262$.

The transpiler is optimizing within the constraints your circuit gave it. Those constraints are yours to choose, and they are worth more than the optimizer.

Note also the linear rows: level 3 produces a deeper circuit (54 vs 41) with the same gate count, and scores better (0.9310 vs 0.9116). Chapter 28 §28.3 found the opposite direction on a different circuit. Which proxy wins is circuit-specific, which is the argument for measuring rather than reasoning.

★ What actually changed at level 3, and it is neither proxy

That last paragraph frames the linear rows as depth versus gate count. Look at what the transpiler actually did, and neither proxy is doing the work:

   level   layout chosen                        2q survival   ecr   depth   rz
     0     [  0,   1,   2,   3,   4,   5]            0.9587    15     106   267
     1     [  0,   1,   2,   3,   4,   5]            0.9587    15      41    78
     2     [125, 124, 123, 122, 121, 120]            0.9720    15      54    83
     3     [125, 124, 123, 122, 121, 120]            0.9720    15      54    83

The two-qubit gate count is identical at every level. The depth got worse. And the circuit moved to a different part of the chip.

   level 1, qubits   0 -   5    edge errors  0.0075  0.0088  0.0087  0.0070  0.0100
   level 3, qubits 120 - 125    edge errors  0.0056  0.0063  0.0049  0.0053  0.0063

(Level 3 writes the chain in either direction depending on the seed — 20 of 24 seeds give [125,...,120] and 4 give [120,...,125]. Same six qubits, same five edges, same survival.)

Every one of the five edges is better on the level-3 qubits. That is not luck: optimization levels 2 and 3 run VF2PostLayout, which re-scores the chosen embedding against the calibration record and moves the circuit if it finds better qubits. Level 1 stops at the first perfect structural embedding it finds — which on a chain of a chip whose qubits are numbered from zero is [0,1,2,3,4,5].

Note also where the change happens: between level 1 and level 2, not between 2 and 3. Levels 2 and 3 produce the same layout, the same 15 ecr, the same 83 rz, the same depth 54. Chapter 28 §28.3 measured levels 2 and 3 as statistically indistinguishable on a different circuit; here they are identical.

This is a small correction to the framing above, and it points the same way as the rest of the chapter: part of what "optimization level" buys you is not optimization at all. It is layout selection — the thing §29.4 is about to lose money trying to do by hand.

📉 Noise Report: what the extra 0.0194 is made of.

The level-3 circuit runs on better qubits in two separate ways, and only one of them is in the coupling map's neighbourhood:

text qubit set 2q survival P(all 6 readouts correct) product level 1 [ 0 .. 5] 0.9587 0.8580 0.8226 level 3 [120 .. 125] 0.9720 0.9399 0.9136

Readout moved six times more than the gate errors did — $+0.0819$ against $+0.0132$. The level-1 set contains a qubit with a 6.05% readout error; the level-3 set's worst is 2.15%.

But now read the prediction honestly. The product model says level 3 should win by $+0.0910$. It won by $+0.0194$ — the right sign, and 4.7× too large.

The reason is a category error that is easy to make and worth naming: the product of survival probabilities is $P(\text{nothing went wrong})$, and the score is $1 - \text{TVD}$. They are not the same quantity. A circuit that suffers one bit-flip does not produce a uniformly random distribution; it produces a distribution that still overlaps the correct one substantially, and TVD credits that overlap. Any model built out of survival probabilities will overstate the damage, and §29.4 is where that overstatement becomes a wrong decision rather than a wrong number.

💰 Cost and Queue: what this table cost, and what the shape change costs.

One row of §29.3's table is 5 seeds × 20,000 shots = 100,000 shots. Chapter 31 scheduled this exact circuit — linear entanglement, level 2, depth 54, 15 ecr — and measured its duration at 7.10 µs. So one row is $100{,}000 \times 7.10\,\mu s = 0.71$ s of device time, and the full six-row sweep is 600,000 shots whose cost is dominated by the two full-entanglement rows at six to ten times the depth.

Now the queue. Chapter 39 §39.3 measured a 6.92 ms job at a five-minute queue running at a utilization of $2.31\times10^{-5}$ — 43,340× wall clock. Submitted the obvious way, as 30 separate jobs, this table is two and a half hours of queueing for a few seconds of computing. Submitted as one batch it is one queue wait. Chapter 39's advice to count jobs before counting gates applies to your own experiments first.

And then the part that makes this chapter unusual. Chapter 39 §39.4 measured that a per-shot price does not depend on circuit depth and a per-minute price does. The hardware-aware circuit uses the same number of shots as the naive one and six to ten times less device time. So:

text pricing model cost of switching to linear entanglement fidelity gained per shot identical +0.1658 per minute lower +0.1658 credits (per job) identical +0.1658

Every other improvement in this book is bought with shots, wall time, or classical compute. This one is bought by changing a string in a constructor.

Where this conclusion would flip

The measurement is real and it is not universal. Four conditions reverse or dissolve it, and knowing which one you are in is more useful than the headline.

1. All-to-all hardware. On trapped ions (Chapter 17) there is no coupling map to match — every pair interacts directly, §29.2's overhead column collapses to 1.0 for all three patterns, and the shape lever disappears entirely. Chapter 17's arithmetic is the honest version of the trade: at the 3.18× overhead measured there, ions win a connectivity-hungry circuit whenever their two-qubit error is below $1-(0.9925)^{3.18} = 2.4\%$. This chapter's advice is a superconducting-architecture result, and Exercise 29.32 asks you to confirm how little of it survives the move.

2. A circuit whose interaction graph already embeds. If your routing overhead is already 1.0, shape is worth exactly zero, because there is nothing left to match. The linear rows are the demonstration: once you are embedded, optimization level is the only lever you have, and it is worth $+0.0194$. The size of the shape effect is a measure of how wrong your circuit currently is, not a constant of nature.

3. A problem whose interaction graph is fixed. For QAOA (Chapter 37) the entangling pattern is the problem instance and you may not change it. The lever moves down one level, to which problem vertex sits on which qubit — a graph-embedding problem rather than a graph-design one, and Exercise 29.24's subject.

4. Cheaper SWAPs. A SWAP costs three two-qubit gates on this basis, which is where the 102 routing gates come from: $102/3 = 34$ SWAPs. On an architecture with a native SWAP, the same routing would cost 34 gates, and the full-entanglement circuit would be $45 + 34 = 79$ hardware gates instead of 147 — an overhead of 1.76× instead of 3.27×. That is arithmetic, not a measurement; what it would do to fidelity is a prediction and not a result, but the direction is clear enough to say that this chapter's factor of six is partly a fact about gate decompositions and not only about topology.

29.4 Choosing your own qubits, and losing

If matching the chip's shape is worth this much, choosing the chip's qubits should be worth something too. Chapter 12 measured a 288× spread in two-qubit gate error and layout scores of 0.9727 against 0.2844.

So: find a connected 6-qubit chain and pin the circuit to it with initial_layout.

   a 6-qubit connected chain on this chip: [7, 6, 5, 4, 3, 2]

It is a valid path. Every consecutive pair is an edge in the coupling map. The linear ansatz maps onto it exactly, with zero routing.

   linear entanglement, level 1, auto layout               15   41   0.9116
   linear entanglement, level 1, STRUCTURE-only layout     15   35   0.6790

The hand-chosen layout lost by $-0.2326$ — a catastrophic regression, from a change that looked like pure improvement and produced a shallower circuit.

The reason is visible immediately in the calibration data:

   my chain [7,6,5,4,3,2]
     edge errors:  1.0000  1.0000  0.0100  0.0070  0.0087
     worst edge 1.0000    survival over 5 edges = 0.0000

   transpiler's automatic layout [0,1,2,3,4,5]
     edge errors:  0.0075  0.0088  0.0087  0.0070  0.0100
     worst edge 0.0100    survival over 5 edges = 0.9587

Two of the five edges have error rate 1.0000. They are dead links — uncalibrated or failed in this snapshot. My path traversed two of them, giving a predicted survival probability of exactly zero.

⚠️ Common Pitfall: a connected path is not a usable path.

The coupling map tells you which qubits can interact. It does not tell you which pairs work. Those are different questions answered by different data, and a graph search over the coupling map alone will happily route your circuit through hardware that is broken.

This is Chapter 12 §12.4's layout-scoring lesson in its sharpest form: the structure is public and the quality is measured, and only one of them is in the coupling map.

How much of the chip is like this

Two dead edges out of five sounds like spectacular bad luck. Enumerate the whole chip and it is not:

   undirected edges                                144
   dead edges (ecr error = 1.0000)                   9   (6.25%)
   (5,6) (6,7) (8,9) (8,16) (52,56) (56,57) (83,84) (84,85) (92,102)

   distinct connected 6-qubit chains               434
   chains containing at least one dead edge         79   (18.2%)
   usable chains                                   355   (81.8%)

   survival over all 434 chains      min 0.0000   median 0.9567   max 0.9773
   survival over the 355 usable      min 0.8570   median 0.9596   max 0.9773

Nearly one connected 6-chain in five is unusable, and a graph search that does not read the calibration record has roughly a one-in-five chance of handing you one. My [7,6,5,4,3,2] picked up two of them because the dead edges (5,6) and (6,7) are adjacent — qubit 6 has both of its low-numbered links dead — and a chain walking down from 7 goes straight through the pair.

That clustering is worth noticing, because it cuts the other way too. If the nine dead edges were scattered independently, a 5-edge chain would avoid them all with probability $(1 - 9/144)^5 = 0.724$, so 27.6% of chains would be hit. Only 18.2% are, because the dead edges share qubits — (5,6) with (6,7), (8,9) with (8,16), (52,56) with (56,57), (83,84) with (84,85) — and a cluster of failures takes out fewer distinct paths than the same number spread around. Broken hardware is correlated, in the direction that flatters the statistics and punishes the unlucky.

These are the same nine edges Chapter 30 §30.3 uses to make its point about statistics: excluding them gives a median two-qubit error of 0.00750 and a mean of 0.01018; including them takes the mean to 0.07205, a factor of 7.1, from 6.25% of the edges. The dead links are simultaneously the reason a quoted device fidelity is ambiguous and the reason a hand-picked layout can score zero.

📐 Math Aside: the survival product is the sum of the errors, until it isn't.

Expanding the product for small errors:

$$\prod_{i}(1-e_i) = 1 - \sum_i e_i + \sum_{i

and the second-order term is available in closed form from the first two power sums, $\sum_{i

text chain sum e 1 - sum e + 2nd order exact product transpiler [0..5] 0.0420 0.9580 0.9587 0.9587 error-aware [72,...,41] 0.0238 0.9762 0.9764 0.9764

Two terms reproduce the exact product to four decimal places. Which is a stronger statement than it looks, because it means the survival metric is linear in the edge errors at these rates: ranking chains by their survival product is the same as ranking them by the plain sum of their edge errors.

A linear metric cannot express "one terrible edge is worse than five mediocre ones." Five edges at 0.0084 and one edge at 0.042 alongside four perfect ones both give $\sum e = 0.042$ and both score 0.9587 — and they are not the same circuit, because the bad edge's error lands on a specific pair of qubits at a specific point in the circuit.

And the expansion fails completely at exactly the interesting point. For my chain, $\sum e = 2.0257$, so the linear form gives $1 - \sum e = -1.03$: not a probability, not a bound, not anything. The exact product is 0.0000. A dead link is not a large error; it is a different regime, which is why edge_error in the project module returns 1.0 for an unusable pair rather than raising — a truthful zero downstream beats an exception in a helper.

Fixing the mistake — and still losing

Search all connected 6-chains, scoring by measured two-qubit error:

   best connected 6-chain by measured survival: [72, 62, 61, 60, 53, 41]   survival 0.9764
   transpiler's automatic layout:                                          survival 0.9587

By this metric my chain is now better than the transpiler's, by 1.8%. Run it:

   linear entanglement, level 1, auto layout            0.9116
   linear entanglement, level 1, ERROR-AWARE layout     0.8959

It still loses, by $-0.0157$ — small, but about four standard errors and in the wrong direction from what the survival score predicted.

The survival heuristic — the product of two-qubit gate errors along the path — is an incomplete model. It ignores readout error, $T_1$ and $T_2$ on the specific qubits, single-qubit gate errors, and the scheduling that follows layout selection. Qiskit's VF2Layout and VF2PostLayout score candidate embeddings against the full error model, and they are simply better at it than one hand-built number.

★★ Which missing term did it? Readout, and adding it flips the prediction

"Incomplete model" is a diagnosis, not an explanation. Pull the readout errors for the six qubits in each layout and multiply them the same way:

   layout                                 2q survival   P(all 6 readouts correct)   product
   transpiler's automatic  [ 0, 1, 2, 3, 4, 5]  0.9587                     0.8580    0.8226
   hand-picked error-aware [72,62,61,60,53,41]  0.9764                     0.8248    0.8053

The hand-picked chain wins on gate errors and loses on readout, and the readout term is larger.

   readout errors on [72, 62, 61, 60, 53, 41]:
      0.0972   0.0125   0.0308   0.0105   0.0264   0.0093

The chain search bought a 1.85% relative improvement in two-qubit survival and paid for it with qubit 72, whose readout is 9.72% wrong — a 3.87% relative loss on the readout term. The extended model predicts the transpiler's layout ahead by $+0.0172$.

The measurement said $+0.0157$.

That is the right sign and the magnitude to within 0.0015, and it is worth being careful about how much credit to give it. Applied to §29.3's level-1-versus-level-3 comparison the same extended product predicted $+0.0910$ against a measured $+0.0194$ — the right sign, 4.7× too big. Applied to the structure-only chain it predicts $0.0000 \times 0.6277 = 0.0000$ against a measured 0.6790.

   comparison                        extended model   measured    verdict
   auto vs error-aware chain                +0.0172    +0.0157    sign and size
   level 1 vs level 3 (linear)              +0.0910    +0.0194    sign only
   auto vs structure-only chain             +0.8226    +0.2326    sign only

🔬 Honest Assessment: readout explains the surprise; it does not rehabilitate the metric.

One correct sign-and-magnitude prediction out of three is a hypothesis, not a validated model, and the book's own rule applies: a result from one or two samples is a draw from a distribution.

What the readout term does establish is which omission mattered. Not $T_1$/$T_2$ — the level-3 layout has a worse minimum $T_2$ than the level-1 layout (15.7 µs against 78.9 µs) and won anyway, which is Chapter 31 §31.2's finding that this device is gate-limited rather than coherence-limited, arriving from the layout side.

It was readout, and readout is the term everybody omits, because two-qubit gate error is the number on the spec sheet. Chapter 30 §30.9 makes the same point from the benchmarking side — check readout separately, randomized benchmarking cannot see it, and 12 of 127 qubits on this chip are above 10%. A chain search that reads target["ecr"] and never reads target["measure"] is optimizing five numbers and ignoring six.

The search was not exhaustive either

One more correction, in the chapter's own direction. "Search all connected 6-chains" describes what the code was trying to do rather than what it did: best_chain_by_survival extends one greedy path from each starting qubit, so it examines 127 candidates. The chip has 434.

Enumerating all of them:

   best over 127 greedy chains    [72, 62, 61, 60, 53, 41]   survival 0.9764
   best over all 434 chains       [58, 59, 60, 61, 62, 72]   survival 0.9773

The exhaustive search finds a chain better by 0.0009 — under a third of the seed-to-seed scatter on the row it would have changed ($\sigma = 0.0028$), and roughly one-seventeenth of the amount by which the metric mispredicted the outcome.

That ratio is the whole lesson in one number. Making the search exhaustive would have improved the objective by 0.0009 while the objective was wrong by 0.0157. Effort spent perfecting a proxy is bounded by how good the proxy is, and nobody measures that first because the search is the part that feels like engineering.

🔬 Honest Assessment: choose the circuit's SHAPE; leave the LAYOUT to the transpiler.

Shape is where your knowledge is irreplaceable — you know your algorithm's interaction graph, and the transpiler can only take it as given. Worth +0.1658.

Layout is where the transpiler's knowledge is irreplaceable — it reads the whole calibration record and scores embeddings against all of it. Hand-picking cost −0.0157 when done carefully, and −0.2326 when done by graph structure alone.

"Hardware-aware programming" naturally suggests taking control of both. The measurement says take control of one.

Use initial_layout when you have information the transpiler does not — a qubit you know is recalibrating, a region reserved for another job, a result you need to reproduce exactly. Not as a general-purpose optimization.

Calibration staleness: why a pinned layout is different in kind

There is a second argument against pinning, and it is stronger than the measurement.

Every number in this section has a timestamp. FakeSherbrooke is a frozen snapshot; a real device is recalibrated on a schedule, and after each recalibration the nine dead edges are a different nine, the 0.00750 median is a different number, and qubit 72's 9.72% readout is whatever it is today. Chapter 30 §30.9 states the rule as an instruction: re-pull the calibration; it is a timestamp, not a property.

Now notice the asymmetry that creates.

Every input to compilation except initial_layout is re-derived when you recompile. Re-run transpile() tomorrow and the basis translation, the routing, and — crucially — the layout are all recomputed against tomorrow's Target. A hard-coded initial_layout=[72, 62, 61, 60, 53, 41] is not recomputed. It is a decision made against one snapshot, frozen into source, and still there on the morning that edge (60, 53) joins the dead list.

A pinned layout is the only part of your compilation that cannot be refreshed by recompiling.

And the exposure window is not the gap between your two runs. It is the gap between when you read the calibration and when your circuit executes, which on a cloud platform includes the queue. Chapter 39 §39.6 is the productized form of exactly this: the platform assigns physical qubits at execution time, using data that may have been refreshed after you submitted, and §39.8's metadata list — backend, job ID, execution timestamp, calibration snapshot, final physical qubits, transpiler version and level and seed, shots, mitigation — exists because without it you cannot tell a real effect from a recalibration.

Three practices follow, and they cost almost nothing:

Check usability at submission time, not design time. usable_path is one Target lookup per edge. Running it just before you submit costs microseconds; discovering a dead link afterwards costs the run. This is Chapter 12 §12.3's preflight idea, applied to the layout rather than the circuit.

If you pin, pin with an expiry and a reason. A layout in source without the date and backend it was chosen on is a landmine with your name on it. The project module's recommend_layout enforces the reason; the date is yours to record.

Prefer re-transpiling over caching a transpiled circuit. Caching an ISA circuit caches its layout, which converts a transient calibration reading into a permanent one.

The sharpest statement of the whole section is this: the transpiler's automatic layout has an expiry of zero. It is chosen fresh from whatever the Target says at the moment you compile. No hand-picked layout can have that property, and it is worth considerably more than the 1.8% survival advantage my chain briefly appeared to have.

🗝️ Version Note: where this chapter's data lives in Qiskit 2.x.

The APIs this chapter reads have moved, and one of them is gone entirely.

text qiskit.pulse REMOVED in Qiskit 2.0 (ModuleNotFoundError) backend.defaults() gone with it, along with instruction_schedule_map, add_calibration, .calibrations, drive_channel backend.target["ecr"][(a,b)] .error and .duration -- the live source backend.target["measure"][(q,)] .error -- the readout term nobody reads backend.qubit_properties(q) .t1, .t2, .frequency coupling_map.neighbors(q) DIRECTED -- successors only coupling_map.graph.neighbors_undirected(q) what you almost always want

The error data survived the pulse removal. Everything §29.4 needs is in the Target, which is the modern single source for basis gates, coupling, durations, and error rates. Chapter 31 is the chapter about what was lost; this one is unaffected.

Two more, measured on Qiskit 2.5.1:

• EfficientSU2 the class is deprecated as of Qiskit 2.1, along with TwoLocal, NLocal and BlueprintCircuit. The replacement is the lowercase function efficient_su2(n, reps=, entanglement=), which is what this chapter's code uses and what returns a plain QuantumCircuit.
• transpile() is not deprecated in 2.5.1 — it emits no warning — but generate_preset_pass_manager is the entry point that lets you introspect and modify the stages, which is Chapter 28 §28.5's subject and the only way to see the layout passes discussed above.

29.5 Designing for the interaction graph

If shape is the lever, what does pulling it look like?

Prefer linear or grid entanglement in variational ansätze. Chapter 16 and Chapter 24 used EfficientSU2 and hardware-efficient circuits throughout. The entanglement parameter is the single highest-leverage setting in that whole family, and §29.2 measured linear at 1× overhead against full at 3.3×.

Do not close the ring unless you need it. circular cost 36 extra gates for one edge. If your problem is genuinely cyclic, pay it; if the ring was decorative, it is the most expensive decoration available.

Reorder your problem to match the chip. For QAOA (Chapter 24 §24.4), the interaction graph is the problem graph, and you cannot change it — but you can choose which problem vertex sits on which qubit. That is a graph-embedding problem, and a good embedding is worth more than any transpiler pass.

Use the chip's native gates. Chapter 17 measured how framework abstractions hide the native basis: ecr here, cz on other superconducting devices, MS and GPi on trapped ions. A circuit written in cx on an ecr machine pays a translation on every gate. It is usually a small constant, and it is free to avoid.

Consider mid-circuit measurement and reuse. Chapter 9's dynamic circuits and Chapter 25 §25.7's feedforward allow a qubit to be measured, reset, and reused. On a device where qubit count is the binding constraint this converts width into depth — a real trade, and one only you can evaluate.

★ Shape buys reproducibility, not just fidelity

There is a second payoff that does not show up in a fidelity table at all. Transpile all three shapes at 24 seeds and record what changes:

   shape      level   distinct layouts / 24    ecr range    depth range
   linear         1                       1      15 -  15     41 -  41
   linear         3                       2      15 -  15     54 -  54
   circular       1                      12      60 -  72    124 - 252
   circular       3                       9      52 -  72    150 - 291
   full           1                      16     135 - 165    310 - 408
   full           3                      10     110 - 132    311 - 462

The hardware-aware circuit compiles to the same thing every time. One layout across 24 seeds, identical gate count, identical depth. (The two layouts at level 3 are the same six qubits written forwards and backwards, with identical counts — cosmetic.)

The naive circuit does not. At level 1 its two-qubit count spans 135 to 165 and its depth 310 to 408, from nothing but the seed. And the ring's spread is the worst of the three even though its circuits are the smaller ones: depth 124 to 252, a factor of 2.03, against the complete graph's factor of 1.32.

Chapter 10 §10.9 argued that an unseeded transpilation is unreproducible by its own author. This is the sharper version: whether the seed matters at all is a property of your circuit's shape. A circuit whose interaction graph embeds gives SABRE nothing to be random about — VF2Layout finds a perfect embedding, the routing pass has no SWAPs to choose between, and the heuristic search never runs.

That refines a conclusion drawn elsewhere in this book, and the refinement is worth stating plainly. Chapter 39 §39.6 measured layout roulette: a 14-qubit EfficientSU2 across 24 seeds gave fidelities from 0.5755 to 0.7911 — 2.03× the error — with two-qubit counts from 49 to 112. The same test on a 4-qubit circuit produced exactly zero variation, and Chapter 39 concludes that layout variance is a large-circuit phenomenon.

Look at the two circuits. The 14-qubit one is entanglement="circular" — a ring, which §29.2 shows does not embed. The 4-qubit control is a plain cx chain — a path, which does. The two experiments differ in width and in shape, so the attribution to width is confounded.

The table above decouples them. Every row is six qubits on the same chip in the same run, and the variance appears and disappears with the shape alone: zero for the path, twelve distinct layouts for the ring. Layout roulette is an embeddability phenomenon, not a size phenomenon — size matters only because wide circuits are less likely to embed.

Which makes the practical rule stronger than "record your seed":

If your routing overhead is 1.0, the seed cannot hurt you. If it is not, the seed is an uncontrolled variable in every result you report.

🧪 Run It: find out in ninety seconds whether this chapter applies to you.

Take a circuit you actually run, and a backend you actually use.

1. Measure the overhead. Two counts and a division:

python logical = sum(qc.decompose().count_ops().get(g, 0) for g in ("cx", "cz", "ecr")) isa = transpile(qc, backend, optimization_level=1, seed_transpiler=0) hardware = sum(isa.count_ops().get(g, 0) for g in ("cx", "cz", "ecr")) print(hardware / logical)

1.0 means routing is free and this chapter has nothing for you — go and read Chapter 28, optimization is your only remaining lever. An overhead of 2 means half of what runs on the device is not your algorithm; §29.2's full-entanglement circuit was at 3.27, which is 69%.

2. Measure the seed spread. Loop seed_transpiler from 0 to 7 and print the gate count and depth each time. If step 1 gave you 1.0, expect eight identical rows. If it did not, expect a spread — and every unseeded result you have ever reported on this circuit was one draw from it.

3. Change one string. If your ansatz is from the hardware-efficient family, set entanglement="linear" and repeat steps 1 and 2. §29.3 measured that change at $+0.1658$ in output fidelity — six times what the entire optimization stage was worth — and §29.6 is the argument you should have with yourself before keeping it.

4. Check the layout you were given, not the one you assumed. isa.layout.final_index_layout(), then look up each edge in backend.target["ecr"] and each qubit in backend.target["measure"]. If anything reads 1.0, you have found a dead link before it found you.

29.6 What this does not fix

The linear ansatz scores 0.9310 at level 3. That is genuinely good, and it is worth being precise about what has been achieved.

It is a 6-qubit circuit with 15 two-qubit gates. Chapter 28's Grover-like circuit had 257 and retained 12.9%. Hardware-aware design did not make noise stop mattering; it made this circuit small enough that noise matters less.

And the expressibility question is now open. Chapter 16 §16.6 discussed ansatz design and barren plateaus. A linear entanglement pattern is less expressive than all-to-all — it generates a smaller family of states — so the right comparison is not "same ansatz, cheaper" but:

   full entanglement:   more expressive, 0.7720 fidelity
   linear entanglement: less expressive, 0.9310 fidelity

Which is better depends on whether the extra expressibility reaches states your problem needs. For Chapter 24's H₂ ansatz the answer was that a four-parameter problem-informed circuit reached machine precision, and expressibility was not the constraint. For a harder molecule it might be.

The honest framing: hardware-aware design trades algorithmic reach for fidelity, and on current devices that trade is usually worth making — because a more expressive circuit you cannot execute is not more expressive.

Chapter 16 §16.6 also found that problem-informed ansätze are the main defence against barren plateaus, and Chapter 24 §24.4 noted QAOA gets one for free. Those arguments point the same way as this chapter's, which is some comfort: the ansatz that runs is often also the ansatz that trains.

The failure modes, and how each one announces itself

Every one of these was hit while writing this chapter, or measured while writing it.

Reading coupling_map.neighbors() as undirected. Symptom: a degree distribution whose sum equals $|E|$ rather than $2|E|$; here, 29 qubits with no neighbours at all. Fix: union both directions, or graph.neighbors_undirected().

Believing a connected path is a usable path. Symptom: every structural metric improves — fewer gates, shallower circuit — and the fidelity collapses. 18.2% of this chip's connected 6-chains contain a dead edge. Fix: usable_path against target["ecr"], at submission time.

Ranking layouts with a two-qubit error product. Symptom: your metric says you beat the transpiler and the measurement says you lost. Fix: use the product to reject obviously bad paths, never to rank good ones. The metric is linear in the edge errors and cannot see the difference between one bad edge and five mediocre ones.

Reading target["ecr"] and never target["measure"]. Symptom: an optimized layout containing a qubit with 9.72% readout error. Fix: readout lands on every measured qubit exactly once, so it is six numbers on a 6-qubit circuit against the path's five — at least as important, and easier to look up.

Caching a transpiled circuit. Symptom: results drift with no code change, or fail to drift when the device has been recalibrated. Fix: cache the source circuit, re-transpile, record §39.8's metadata.

Inheriting entanglement="full" from a tutorial. Symptom: a routing overhead above 3 and an engineering backlog full of pass-manager work. Fix: Case Study 2's one-minute diagnostic — hardware_2q / logical_2q — before optimizing anything.

Comparing two unseeded runs. Symptom: a 1.32× depth difference that reverses when you re-run it. Fix: fix seed_transpiler, or report a distribution over seeds rather than a number.

Concluding from a small circuit that the transpiler is deterministic. Symptom: a toy benchmark with zero seed variance and a production circuit with plenty. Fix: check the routing overhead, not the qubit count — that is what decides whether the seed matters.

29.7 A policy

   1. CHOOSE THE SHAPE. Match your entangling pattern to the chip's coupling
      graph. Worth +0.1658 here, against +0.0262 for the entire optimization
      stage -- a factor of six.

   2. DO NOT CLOSE RINGS you do not need. One extra edge cost 36 gates.

   3. LEAVE THE LAYOUT ALONE. The transpiler scores embeddings against the
      full calibration record. Hand-picking cost -0.0157 done well and
      -0.2326 done by graph structure alone.

   4. IF YOU DO SET initial_layout, use the CALIBRATION DATA, not the coupling
      map. A connected path is not a usable path -- two of my five edges had
      error rate 1.0.

   5. WRITE IN THE NATIVE BASIS where it is free to do so.

   6. MEASURE. Chapter 28 found level 2 deeper-but-fewer-gates and it did not
      matter; this chapter found level 3 deeper-but-better and it did. Which
      proxy wins is circuit-specific.

   7. ASK WHETHER YOU LOST ANYTHING. Less entanglement is less expressibility.
      Check that the cheaper ansatz still reaches your answer.

What we measured

• FakeSherbrooke is heavy-hex: 127 qubits, 144 undirected edges, maximum degree 3. A complete graph would have 8,001.
• Linear entanglement: 15 logical two-qubit gates → 15 hardware gates. Zero routing overhead. Full entanglement: 45 → 147 at level 1 (3.3×), 116 at level 3.
• circular costs 54 gates for 18 logical — one unnecessary ring-closing edge cost 36 gates.
• ★★★ Hardware-aware at level 1 (0.9116) beats naive at level 3 (0.7720) by $+0.1397$. Isolating the variables: shape at a fixed level is worth $+0.1658$, optimization level at a fixed shape $+0.0262$ — a factor of six.
• ★ A hand-chosen connected chain [7,6,5,4,3,2] scored 0.6790 against the transpiler's 0.9116 — because two of its five edges have error rate 1.0000 and its predicted survival was exactly 0.0000.
• ★ Re-picking with calibration data gave a chain with survival 0.9764 against the transpiler's 0.9587 — and it still measured worse, 0.8959 vs 0.9116. The two-qubit-error product is an incomplete model of what a layout costs.
• On this circuit level 3 is deeper than level 1 (54 vs 41) and scores better — the opposite of Chapter 28's finding on a different circuit.
• The chip's girth is 12: there is no 6-cycle anywhere, so circular on six qubits cannot embed at any layout. $K_6$ needs degree 5 against a maximum of 3, so full cannot embed on any heavy-hex device. Two of §29.2's three rows are settled by graph theory before the transpiler runs. Diameter 26, mean pairwise distance 11.13, and only 1.80% of qubit pairs adjacent.
• 9 of 144 edges are dead (6.25%), and they cluster: 79 of the 434 connected 6-chains (18.2%) contain one, against 27.6% if the failures were independent.
• ★ A noiseless device scores 0.9793, not 1.0000, on this experiment — 20,000 shots over 64 outcomes. So the linear circuit at level 3 recovers 95% of what the measurement could show; and because every row carries the same bias, all the gaps above are unaffected.
• ★★ The level-3 gain on the linear ansatz is a layout change, not an optimization. Identical gate count (15), worse depth (54 vs 41), and a different six qubits: [0..5] survival 0.9587 → [120..125] survival 0.9720, readout-all-correct 0.8580 → 0.9399. It happens at level 2, and levels 2 and 3 are identical. VF2PostLayout is part of what "optimization level" buys.
• ★★ The missing term in the survival heuristic is readout. Adding it, the transpiler's layout scores $0.9587 \times 0.8580 = 0.8226$ against the hand-picked chain's $0.9764 \times 0.8248 = 0.8053$ — predicting the transpiler ahead by +0.0172 against a measured +0.0157. The chain search bought 1.85% on gate survival and paid 3.87% on readout, by selecting a qubit with 9.72% readout error. The extended model gets the sign right on all three comparisons and the magnitude on one; it is a better rejector, not a validated predictor.
• ★ Shape decides reproducibility as well as fidelity. Across 24 seeds: linear gives 1 distinct layout, 15 ecr, depth 41 — every time; full gives 16 layouts, 135–165 ecr, depth 310–408. Chapter 39 §39.6's "layout roulette is a large-circuit phenomenon" is confounded — its varying circuit was circular and its zero-variance control was a cx chain. The variable is embeddability, not width.
• The §29.4 chain search examined 127 greedy candidates, not all 434. Exhaustive enumeration finds survival 0.9773 against the reported 0.9764 — an improvement of 0.0009 in an objective that was wrong by 0.0157.
• A pinned layout is the only compilation input that re-transpiling cannot refresh. Everything else is re-derived from today's Target; initial_layout is a snapshot frozen into source.

The theme: the cheapest optimization is not needing one — and choose the shape, leave the layout, because the knowledge that is irreplaceable is not the same at both levels.