Chapter 17 — Key Takeaways (Amazon Braket)

The Braket page. §17.4's connectivity measurement is the one that changes what you build.

Setup

from braket.circuits import Circuit, Observable, Noise
from braket.devices import LocalSimulator

circuit = Circuit().h(0).cnot(0, 1)          # gate methods RETURN the circuit
LocalSimulator().run(circuit, shots=1000).result().measurement_counts
  {'11': 490, '00': 510}
Backend Use
LocalSimulator("braket_sv") state vector (default) — no AWS account
LocalSimulator("braket_dm") density matrix — required for noise
AwsDevice(arn) real hardware — credentials, and charges per task + per shot

🗝️ Unlike IBM's open tier (Ch. 2), Braket hardware is a paid service. Device availability and pricing change — check current docs. Windows: sys.stdout.reconfigure(encoding="utf-8") before printing a diagram. Verified amazon-braket-sdk 1.125.0.

Endianness — the third data point

  X on qubit 0:  {'10': 100},  state vector [0,0,1,0], index 2
Framework Convention index
Qiskit little-endian 1
Cirq big-endian 2
Braket big-endian 2

Qiskit is the odd one out — 1 of the 3 tested.

Result types attach to the circuit

Circuit().h(0).cnot(0,1).probability()      # [0.5, 0, 0, 0.5]
Circuit().h(0).cnot(0,1).state_vector()     # [0.7071, 0, 0, 0.7071]
Circuit().h(0).cnot(0,1).expectation(Observable.Z() @ Observable.Z(), target=[0,1])
Circuit().h(0).cnot(0,1).amplitude(["00","11"])   # {'00': 0.7071, '11': 0.7071}

Exact at shots=0. amplitude has no equivalent elsewhere — specific state-vector entries by bitstring, without materializing $2^n$.

★★★ Connectivity has a measured price

Star GHZ (qubit 0 entangles with every other) on FakeSherbrooke, 127-qubit heavy-hex:

    n   logical 2q   ECR gates   depth   overhead
    4            3           3      18      1.00x
    8            7          15      63      2.14x
   10            9          27     115      3.00x
   12           11          35     136      3.18x

11 gates requested, 35 executed. 24 are pure SWAP overhead. Depth grows faster than gate count — and decoherence scales with duration (Ch. 11 §11.7).

Control — a nearest-neighbour chain GHZ:

    n = 4, 6, 8, 10, 12   ->   overhead 1.00x at EVERY size

Same state, same qubit count, 3.18× the cost — decided by circuit shape.

The interaction graph is the property

$$\text{chain: max degree } 2 \qquad \text{star: max degree } n-1$$

Heavy-hex gives each qubit 2–3 neighbours. A degree-11 vertex cannot embed in a degree-3 graph without paths, and paths cost gates. This is graph embedding, not a compiler limitation.

On trapped ions: 1.00×, always

Ions share collective vibrational modes; the Mølmer–Sørensen gate couples any two through that shared mode, so connectivity is complete by construction.

  MS(0, 0, pi/2) on |00>  ->  [0.7071, 0, 0, -0.7071i]     populations [0.5, 0, 0, 0.5]

One native gate makes a maximally entangled state. Superconducting needs H + ECR + corrections.

The break-even

$$\varepsilon_{\text{ion}} = 1 - (1 - \varepsilon_{\text{sc}})^{r}$$

    n   overhead r   break-even error for all-to-all
    4        1.00x                            0.0075
    8        2.14x                            0.0160
   12        3.18x                            0.0237

At n=12, trapped ions win if their 2q error is below ~2.4% — a bar current ion hardware clears — and the bar loosens as n grows. For a nearest-neighbour circuit the overhead is 1.00× and the faster superconducting gates win.

THE QUESTION IS NEVER "WHICH HARDWARE IS BETTER." IT IS "WHAT SHAPE IS MY CIRCUIT."

⚛️ Why connectivity is physical

Superconducting: fixed circuits coupled by fabricated resonators. Two qubits interact iff someone etched a coupler; you cannot etch all pairs (wiring, crosstalk). The lattice is a manufacturing constraint.

Trapped ions: atoms in a trap, interacting through shared motion — a global degree of freedom. The graph is complete because the coupling bus is shared.

The trade is speed. SC gates: ns. Ion gates: μs (~100× slower). Ion coherence is correspondingly longer, so gate count before decoherence is comparable — wall-clock is not.

Native gates and verbatim boxes

Braket exposes 41 gates, including hardware-specific ones:

Gate Hardware
MS, GPi, GPi2 trapped ion (IonQ)
XY, CPhaseShift superconducting (Rigetti)
ECR superconducting (IBM) — Part II's gate
PulseGate pulse-level control
Circuit().add_verbatim_box(Circuit().rz(0, 0.1).rz(1, 0.2))

Runs exactly as written — no translation, no routing, no optimization. The escape hatch Part II lacked (Ch. 10's unasked-for choices; Ch. 13 CS2's silently-inert pass). Essential for benchmarking (Ch. 30) and QEC circuits that must not be "optimized."

⚠️ Inside a verbatim box you are the compiler. You get an error for a non-native gate — the good case. The bad case is a circuit that runs and is worse than the compiler's version. Use for control, not performance: Ch. 10 measured the transpiler beating hand-written layouts.

The modality table

Superconducting Trapped ion Neutral atom
Connectivity fixed lattice +SWAPs all-to-all reconfigurable
Gate speed ns μs (~100× slower) μs
Coherence ~100s of μs seconds ~seconds
Qubits today ~100–1000+ ~30–50 100s–1000s
Uniformity poor — 288× spread excellent excellent
Native 2q ECR/CZ MS Rydberg blockade
Best for deep local circuits connectivity-hungry large-scale analog

★ Uniformity. Chapter 12's whole apparatus — device health, layout scoring, preflight — answers fabrication variability. Ion traps have no dead qubit 84; every ion of a species is identical by physics.

Neutral atoms add analog Hamiltonian simulation: arrange atoms, engineer a Hamiltonian, let it evolve. Not universal gate-model — and for Ising-type problems it reaches sizes the gate model cannot.

Noise transfers exactly

  channel                    error fraction   imbalance
  depolarizing 0.05                  0.0630     +0.0042
  bit flip 0.05                      0.0930     +0.0008
  phase flip 0.05                    0.0000     +0.0012
  amplitude damping 0.15             0.1073     +0.3228
  phase damping 0.30                 0.0000     -0.0068

Chapter 11 §11.7's signature table, reproduced in a third framework. Phase damping and phase flip invisible in Aer, Cirq, and Braket alike — the computational basis is blind to phase in every framework, because it is a fact about measurement.

🔬 Portability of code ≠ portability of results

Transfers Does not transfer
circuit construction · result types · noise semantics · correctness cost · which failure modes exist · feasibility

An abstraction that unifies an interface implies the things behind it are interchangeable. When they are not, the abstraction is making an argument, and the argument is wrong.

Fourth instance: readout_error=0.5 (Ch. 12) · dd.enable=True (Ch. 13) · counts={'01':…} (Ch. 14) · AwsDevice(...) (here). None lied. Each answered the question it was asked.

Common pitfalls

  • Optimizing within a topology before measuring the overhead of it.
  • Assuming Part II's lattice constraints are facts about quantum computing.
  • Reading a one-line device swap as a free choice.
  • Using verbatim boxes for performance rather than control.
  • Running a noiseless circuit on braket_dm (Braket warns; Ch. 11 measured the penalty).
  • Forgetting ion gates are ~100× slower when the workload is variational.

Project piece added this chapter

vqelab/topology.pyinteraction_graph(), interaction_degree(), connectivity_overhead() (transpiles against the target and all-to-all), breakeven_error_rate(), and recommend_modality() which must cite a number. 13 tests pass, including test_nearest_neighbour_circuit_is_free_on_a_line, test_star_circuit_overhead_grows_with_size, and test_a_recommendation_always_carries_its_evidence.