Chapter 29 — Key Takeaways (Hardware-Aware Programming)

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Chapter 29 — Key Takeaways (Hardware-Aware Programming)

The cheapest optimization is not needing one.

The chip is not a complete graph

   FakeSherbrooke: 127 qubits, 144 undirected edges
   degree distribution: {1: 2, 2: 89, 3: 36}     maximum degree 3
   a complete graph on 127 qubits: 8,001 edges

Heavy-hex, and the low connectivity is deliberate — fewer neighbours means less crosstalk, and crosstalk is harder to fix than routing. Every two-qubit gate between non-adjacent qubits must be routed, as SWAPs costing three two-qubit gates each.

★ Shape decides the routing bill

EfficientSU2(6, reps=3), identical except for which pairs get entangled:

   entanglement                logical 2q   L1 ecr   L3 ecr   overhead
   full (all-to-all)                   45      147      116       3.3x
   circular                            18       69       54       3.8x
   linear (matches a chain)            15       15       15       1.0x

Linear: 15 logical → 15 hardware. Zero routing overhead — a graph embedding, not a routing problem. Full: 45 → 147, and level 3 only grinds it to 116.

⚛️ Routing overhead is a property of your circuit, not of the transpiler. If the graphs match, the job is free. If not, the cost is set by how badly they mismatch, and optimization only finds a cheaper route through the same mismatch.

circular is linear plus one ring-closing edge that is not on the chip: 15 → 69 gates. One edge you did not need cost more than the fifteen you did.

★★★ Shape beats optimization, by six times

5 transpiler seeds × 20,000 shots on a device noise model, scoring $1-\text{TVD}$:

   configuration                                        ecr  depth   1-TVD     std
   full entanglement,   level 1, auto layout            147    396  0.7458  0.0057
   full entanglement,   level 3, auto layout            118    334  0.7720  0.0054
   linear entanglement, level 1, auto layout             15     41  0.9116  0.0028
   linear entanglement, level 3, auto layout             15     54  0.9310  0.0051

Hardware-aware at LEVEL 1 (0.9116) beats naive at LEVEL 3 (0.7720) by $+0.1397$.

Isolating the variables:

   optimization level, shape held fixed  (naive L1 -> naive L3):  +0.0262
   circuit shape, level held fixed       (naive L1 -> aware L1):  +0.1658

🔬 Shape is worth SIX TIMES the optimization level. The transpiler optimizes within the constraints your circuit gave it. Those constraints are yours to choose, and they are worth more than the optimizer.

And note: level 3 here is deeper than level 1 (54 vs 41) and scores better — the opposite of Chapter 28's finding on a different circuit. Which proxy wins is circuit-specific.

★★ ...but choosing your own qubits loses

   linear entanglement, level 1, auto layout               15   41   0.9116
   linear entanglement, level 1, STRUCTURE-only layout     15   35   0.6790   (-0.2326)

A hand-picked connected chain [7,6,5,4,3,2], producing a shallower circuit, lost catastrophically:

   my chain:               1.0000  1.0000  0.0100  0.0070  0.0087   survival 0.0000
   transpiler's [0..5]:    0.0075  0.0088  0.0087  0.0070  0.0100   survival 0.9587

⚠️ A connected path is not a usable path. Two of the five edges have error rate 1.0000 — dead links. The coupling map says which qubits can interact; the calibration record says which pairs work. A graph search over the coupling map routes through broken hardware without complaint.

And fixing that still loses:

   best chain by measured survival [72,62,61,60,53,41]:  survival 0.9764  (beats 0.9587!)
   MEASURED fidelity:                                    0.8959  vs 0.9116   (-0.0157)

The survival product ignores readout error, $T_1$/$T_2$ on the specific qubits, single-qubit errors, and post-layout scheduling. VF2Layout scores against the full error model.

🔬 CHOOSE THE SHAPE, LEAVE THE LAYOUT.

Shape: your knowledge is irreplaceable — you know your interaction graph. Worth +0.1658. Layout: the transpiler's knowledge is irreplaceable — it reads the whole calibration record. Hand-picking cost −0.0157 done carefully, −0.2326 done by graph structure alone.

"Hardware-aware" sounds like taking control of both. The measurement says take control of one.

Set initial_layout only for information the transpiler cannot have: a qubit you know is recalibrating, a reserved region, an exact reproduction, or an experiment where qubit identity is the variable.

Designing for the interaction graph

Prefer linear/grid entanglement in variational ansätze. The entanglement parameter is the highest-leverage setting in the whole hardware-efficient family.
Do not close rings you do not need.
Reorder your problem to match the chip. For QAOA (Ch. 24 §24.4) the interaction graph is the problem — but which problem vertex sits on which qubit is yours to choose.
Use native gates — ecr here, cz elsewhere, MS/GPi on ions (Ch. 17).
Consider mid-circuit measurement and qubit reuse (Ch. 9, Ch. 25 §25.7) — converts width into depth.

What this does not fix

It is a 6-qubit circuit with 15 two-qubit gates. Chapter 28's had 257 and retained 12.9%. Hardware-aware design did not make noise stop mattering; it made this circuit small enough that noise matters less.

And expressibility is now open:

   full entanglement:   more expressive,  0.7720
   linear entanglement: less expressive,  0.9310

Whether the extra expressibility reaches states your problem needs is an empirical question, answerable noiselessly on a simulator in an afternoon. For Chapter 24's H₂ the answer was that four problem-informed parameters reached machine precision — expressibility was not the constraint.

A more expressive circuit you cannot execute is not more expressive.

Ch. 16 §16.6 (problem-informed ansätze defend against barren plateaus) and Ch. 24 §24.4 (QAOA gets one free) point the same way: the ansatz that runs is often the ansatz that trains.

The policy

   1. CHOOSE THE SHAPE. +0.1658 against +0.0262 for the whole optimization stage.
   2. DO NOT CLOSE RINGS you do not need.
   3. LEAVE THE LAYOUT ALONE.
   4. IF YOU DO set initial_layout, use CALIBRATION DATA, not the coupling map.
   5. WRITE IN THE NATIVE BASIS where it is free.
   6. MEASURE -- which proxy wins is circuit-specific.
   7. ASK WHETHER YOU LOST ANYTHING. Check the cheaper ansatz still reaches
      your answer.

Common pitfalls

Treating routing overhead as a transpiler problem rather than a design decision.
Accepting a library default (entanglement="full") as if it were not a choice.
Optimizing downstream of a constraint you could have removed.
Believing a connected path is usable.
Reading coupling_map.neighbors() as undirected — it returns successors only, which made 29 qubits appear to have zero neighbours while drafting §29.1.
Ranking layouts with a two-qubit-error product and trusting the ranking.
Switching to a cheaper ansatz without checking it still reaches the answer.

Project piece added this chapter

vqelab/hardware.py — undirected_neighbours (fixing the directed-adjacency gotcha), edge_error returning 1.0 for unusable pairs so a survival product is truthfully zero, usable_path rejecting dead links, routing_overhead, entanglement_comparison, and recommend_layout, which returns None by default and requires an override_reason naming something the transpiler cannot know. chain_survival is documented and tested as an incomplete model that is known to mispredict. 18 tests pass, including test_linear_entanglement_has_ZERO_routing_overhead, test_one_unnecessary_edge_costs_more_than_all_the_necessary_ones, test_a_connected_path_is_not_a_usable_path, and test_recommend_layout_tells_you_NOT_to_set_one.