Case Study 1: The Programmer Who Out-Thought the Transpiler

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Case Study 1: The Programmer Who Out-Thought the Transpiler

Doing everything right

An engineer has read Chapter 29 §29.2 and taken it seriously. Their variational circuit used all-to-all entanglement out of habit; they switch to entanglement="linear", and the routing overhead drops from 3.3× to 1.0. Fidelity goes from 0.7458 to 0.9116.

This is a real, large, correctly-reasoned win. They have understood the chapter's thesis and applied it.

Then they take the next step, which is where it goes wrong.

The next step

If matching the chip's shape is worth this much, surely choosing the chip's qubits is worth something too. Chapter 12 measured a 288× spread in two-qubit gate error and layout scores of 0.9727 against 0.2844. Leaving qubit selection to a heuristic seems like exactly the kind of abdication this chapter argues against.

So they find a connected chain and pin the circuit to it:

chain = find_connected_chain(backend.coupling_map, length=6)   # [7, 6, 5, 4, 3, 2]
transpile(qc, backend, initial_layout=chain, optimization_level=1)

The reasoning is careful. The chain is genuinely connected — every consecutive pair is an edge in the coupling map. The linear ansatz maps onto it exactly. There is no routing at all. The transpiled circuit is even shallower than the automatic version: depth 35 against 41.

Every structural metric improves.

   linear entanglement, level 1, auto layout               15 ecr   depth 41   0.9116
   linear entanglement, level 1, hand-chosen layout        15 ecr   depth 35   0.6790

A regression of $-0.2326$, from a change that improved every number they were looking at.

What the coupling map does not say

The calibration data, one line:

   my chain [7,6,5,4,3,2]
     edge errors:  1.0000  1.0000  0.0100  0.0070  0.0087
     predicted survival over 5 edges = 0.0000

   transpiler's automatic layout [0,1,2,3,4,5]
     edge errors:  0.0075  0.0088  0.0087  0.0070  0.0100
     predicted survival over 5 edges = 0.9587

Two of the five edges have error rate 1.0000. They are dead links — uncalibrated or failed in this snapshot of the device. The circuit was pinned across two connections that do not work.

⚠️ A connected path is not a usable path.

The coupling map answers "which qubits can interact." The calibration record answers "which pairs work." They are different questions with different answers, and only the first is in the object most people reach for.

A graph search over the coupling map will route your circuit through broken hardware without complaint, because from the coupling map's point of view nothing is wrong.

This is Chapter 12 §12.4's layout-scoring lesson in its sharpest possible form. Chapter 12 measured layout scores of 0.9727 and 0.2844 and made the point that layout choice matters. Here the worst case is not merely bad — it is a predicted survival of exactly zero, and it was selected by a method that looked rigorous.

Fixing it, and still losing

The fix is obvious once the problem is visible: score candidate chains by measured error, not by graph structure. Search every connected 6-chain on the chip:

   best connected 6-chain by measured survival: [72, 62, 61, 60, 53, 41]   survival 0.9764
   transpiler's automatic layout:                                          survival 0.9587

By this metric the hand-picked chain is now better than the transpiler's, by 1.8%. The engineer has used the same data the transpiler uses, applied it correctly, and come out ahead on the score.

   linear entanglement, level 1, auto layout               0.9116
   linear entanglement, level 1, error-aware layout        0.8959

It still loses, by $-0.0157$ — about four standard errors, and in the opposite direction from what the survival score predicted.

Why the second attempt failed

The survival heuristic — the product of two-qubit gate errors along the path — is an incomplete model of what a layout costs. It omits:

readout error, which varies substantially across qubits and lands on every measured qubit;
$T_1$ and $T_2$ on the specific qubits, which set how long the circuit can run there;
single-qubit gate errors, which are smaller individually and far more numerous;
the scheduling that follows layout selection, since where gates land determines what can run in parallel.

Qiskit's VF2Layout and VF2PostLayout score candidate embeddings against the full error model in the backend Target. One hand-built number derived from one error channel does not compete with that, and it is unreasonable to expect it to.

🔬 Honest Assessment: choose the SHAPE, leave the LAYOUT.

Shape is where the programmer's knowledge is irreplaceable. You know your algorithm's interaction graph; the transpiler can only accept it as given. Worth +0.1658 here.

Layout is where the transpiler's knowledge is irreplaceable. It reads the entire calibration record and scores against all of it. Hand-picking cost −0.0157 done carefully and −0.2326 done by graph structure alone.

"Hardware-aware programming" sounds like it means taking control of both. The measurement says take control of one.

When to set a layout anyway

Not never — but for reasons the transpiler cannot know rather than reasons it evaluates better than you:

   * a qubit you know is recalibrating and the Target has not caught up
   * a region reserved for another job on a shared device
   * reproducing an earlier run exactly, for a comparison
   * a hardware experiment where the qubit identity IS the variable

The project module encodes this as the default. recommend_layout returns None unless you supply an override_reason — and when you do, it still checks the resulting chain for dead links and still warns that the survival metric is incomplete.

The lessons

A connected path is not a usable path. The coupling map and the calibration record answer different questions. Any layout logic that reads only the first will eventually route through a dead link.

Check your heuristic against the outcome. The survival product ranked the hand-picked chain above the transpiler's and was wrong. A metric that has never been validated against the thing it predicts is a guess with arithmetic in it — Chapter 28 §28.3's lesson, arriving on the layout side.

Know which knowledge is yours. The engineer's understanding of their circuit's structure was irreplaceable and worth a great deal. Their understanding of qubit quality was a subset of the transpiler's and worth less than nothing.

And notice the shape of the mistake. Both attempts improved every metric being looked at, and the first one produced a shallower circuit. Improving the numbers you are watching is not the same as improving the outcome — which is now the third chapter in a row where that has been the finding.

Reproduce it: code/example-02-shape-beats-optimization.py runs all six configurations and prints the calibration data for both chains; usable_path and recommend_layout in code/vqelab/hardware.py encode the two refusals, and test_a_connected_path_is_not_a_usable_path asserts that the hand-chosen chain is connected, has two dead edges, and has survival exactly zero.