Further Reading: Amazon Braket

Tagged Tier 1 (confident it exists and recommended) and Tier 2 (real and worth seeking, but verify the current version or URL).

The primary sources

• The Amazon Braket developer guide. Circuit construction, result types, local simulators, and the device model. The pricing page is part of the documentation you should read before running anything: unlike IBM's open tier, every task and every shot is billed, and the per-task charge makes many small jobs expensive in a way that is easy to discover accidentally. Tier 1.
• The Braket SDK API reference for Circuit, Gate, and Noise. In particular the full gate catalogue — §17.5's forty-one gates — and which are vendor-specific. Worth skimming end to end once; the presence of MS, GPi, XY, and ECR in one namespace is the clearest single illustration of this chapter's point. Tier 1.
• The Braket documentation on verbatim compilation. What is and is not permitted inside a verbatim box, per device. §17.5's warning is that you become the compiler, and this page is the specification you are then compiling against. Tier 1.
• The Braket Analog Hamiltonian Simulation guide. Neutral-atom AHS: how to specify atom positions, driving fields, and detuning, and what class of problems it addresses. This is genuinely different from everything else in this book — not a gate model at all. Tier 1.
• The Braket examples repository. Worked notebooks per modality, including hardware-specific ones. The trapped-ion and neutral-atom examples are the fastest way to see what the abstraction is hiding. Tier 1.

On trapped ions

• Sørensen and Mølmer, "Quantum computation with ions in thermal motion" (1999), Physical Review Letters 82, 1971. The gate. Read it for why the shared vibrational mode makes arbitrary pairs addressable — §17.4's all-to-all connectivity is a direct consequence, and the paper makes the mechanism concrete. Tier 1.
• Cirac and Zoller, "Quantum Computations with Cold Trapped Ions" (1995), Physical Review Letters 74, 4091. The founding proposal for ion-trap quantum computing. Tier 1.
• Bruzewicz, Chiaverini, McConnell, and Sage, "Trapped-Ion Quantum Computing: Progress and Challenges" (2019), Applied Physics Reviews 6, 021314. The comprehensive review: gate speeds, coherence times, chain-length limits, and the engineering constraints §17.6's table summarizes in one row. Read this before believing any single-number comparison between modalities. Tier 1.
• Any current work on ion-chain scaling and photonic interconnects. The honest counterweight to §17.4's all-to-all result: connectivity is complete within a chain, and chains do not scale indefinitely. How ion systems get large is an open engineering question. Tier 2.

On neutral atoms

• Henriet et al., "Quantum computing with neutral atoms" (2020), Quantum 4, 327. The best overview: Rydberg blockade, reconfigurable geometry, and the analog/digital distinction. Tier 1.
• Ebadi et al., "Quantum phases of matter on a 256-atom programmable quantum simulator" (2021), Nature 595, 227. What analog Hamiltonian simulation actually achieves at a scale the gate model cannot reach. The concrete answer to "why would anyone want a non-universal machine." Tier 1.
• Any recent work on neutral-atom gate fidelities and mid-circuit measurement. The modality is moving fastest of the three, so §17.6's table ages quickest in this column. Tier 2.

On connectivity and its cost

• Any treatment of qubit routing and SWAP-network synthesis. §17.4 measured the cost; this literature is about minimizing it, and connects directly to Chapter 10's transpiler stages. Search for qubit mapping, SWAP insertion, and token swapping. Tier 2.
• Literature on architecture-aware algorithm design. The other half of Case Study 1's conclusion: rather than routing a fixed circuit, restructure the circuit for the topology. Chapter 16's "hardware-efficient ansatz" is the variational instance of this idea. Tier 2.
• Graph embedding and minor-containment theory. The mathematics underneath §17.4's result: a degree-11 vertex cannot embed in a degree-3 graph without dilation, and the dilation is what costs gates. Formal, and it explains why no compiler will ever fix this. Tier 2.

Forward references

• Chapter 29 — writing circuits for a topology rather than routing them onto one, which is Case Study 1's "Option 1" done properly.
• Chapter 30 — where verbatim boxes become essential, because a benchmark of the compiler's output is not a benchmark of the device.
• Chapter 18 — the synthesis of Part III, including where Braket sits among the five.
• Appendix G — the hardware reference, extended to cover all three modalities.

Where to go next. If one thing: Bruzewicz et al. on trapped ions. §17.6's comparison table compresses an enormous amount of engineering into seven rows, and that review is where the rows come from — including the constraints that make the all-to-all advantage less unqualified than §17.4 alone suggests.

If two: add Ebadi et al., because analog Hamiltonian simulation is the one thing in this chapter that does not fit the gate-model framing the rest of the book is built on, and it is worth seeing a machine that is useful without being universal.

Then Chapter 18 — Part III's synthesis, and the practical question it has been accumulating: which of these five do you actually use?