Chapter 3 Further Reading: The x86-64 Architecture
Primary References
1. Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 1 Intel Corporation. Chapters 3-5, 13-15. Free download at intel.com/sdm
Volume 1 is the architectural overview. Chapter 3 covers the basic execution environment: the register set, operand sizes, instruction types, and the memory model. Chapter 4 covers data types. Chapter 13 covers the SSE registers and instruction set. Chapter 14 covers SSE2 (which is the baseline for x86-64 floating-point and SIMD). Read Chapters 3 and 4 alongside this chapter; they are dense but precise. The register diagrams in the Intel manual are the authoritative source for the aliasing behavior.
2. AMD64 Architecture Programmer's Manual, Volume 1: Application Programming AMD Corporation. Chapters 2-3. Free download at developer.amd.com
AMD designed the 64-bit extensions (originally called x86-64, now also called AMD64), so their manual is particularly clear on the extensions specific to 64-bit mode: the new registers R8-R15, the REX prefix encoding, the changes to segment registers in 64-bit mode, and the SYSCALL/SYSRET mechanism. Chapter 2 covers the general-purpose registers with clear diagrams. Chapter 3 covers the RFLAGS register with accurate bit-by-bit descriptions. Cross-reference with Intel's manual for any differences (they're rare but exist).
3. System V Application Binary Interface: AMD64 Architecture Processor Supplement Michael Matz et al. Latest version at gitlab.com/x86-psABIs/x86-64-ABI
The document that defines the calling convention used on Linux, macOS, FreeBSD, and all Unix-like systems on x86-64. This is the standard for which registers are arguments, which are callee-saved, how the stack is structured, how structures are passed by value, and how variadic functions work. If you write any code that calls C functions or is called from C, you need to know this document. The key sections: 3.2 (function calling sequence) and 3.4 (Linux-specific conventions). Free and authoritative.
4. "x86-64 Machine-Level Programming" Randal E. Bryant and David R. O'Hallaron, CMU Technical Report CMU-CS-05-137 Available at cs.cmu.edu
The technical report underlying Chapter 3 of CS:APP. Covers x86-64 register conventions, addressing modes, instruction encodings, and the calling convention in detail. Written at a level appropriate for students who have read CS:APP and want more depth on the architecture specifics. The register notation and convention descriptions are used throughout academic literature on x86-64.
Deeper Architecture Coverage
5. "Intel Microarchitecture Manual" (microarch.pdf) Agner Fog, Technical University of Denmark. Free at agner.org/optimize
While primarily an optimization guide, Agner Fog's Microarchitecture manual describes the internal pipeline structures of every Intel and AMD microarchitecture from Pentium through current generations. For Chapter 3's execution model section: the descriptions of frontend (fetch/decode), backend (execution units, ports), and retirement are described per-microarchitecture. The "loop unrolling" and "instruction cache" sections explain why instruction selection affects performance beyond just instruction count. Essential reading for performance work.
6. "Architecture of the Intel Nehalem Processor" David Kanter, Real World Technologies. Free at realworldtech.com
An unofficial but technically deep analysis of Intel's Nehalem microarchitecture (2008), which established the pipeline structure that continues in modified form through current processors. Covers the fetch unit, decoders, micro-op cache, scheduler, execution units, and retirement unit. Understanding Nehalem's architecture helps reason about performance on any subsequent Intel CPU. Similar articles exist for Sandy Bridge, Haswell, and later architectures on the same site.
7. "Processor Architecture" (WikiChip) Community wiki at wikichip.org
WikiChip maintains technical documentation on current CPU microarchitectures including Intel Core and AMD Zen series. Block diagrams of pipeline stages, cache hierarchy tables, instruction throughput data, and core count/topology information. More current than books (updated as new CPUs are released) and more detailed than Wikipedia. Useful for understanding how the abstract pipeline model from the chapter applies to your specific CPU.
SIMD and Extensions
8. Intel Intrinsics Guide Intel Corporation. Free online at software.intel.com/sites/landingpage/IntrinsicsGuide/
The practical reference for SSE/AVX/AVX-512 instructions, presented as C intrinsic functions rather than assembly mnemonics. Essential for when you're using SIMD instructions: shows the C intrinsic, the assembly instruction, the operation performed, the throughput and latency for Intel microarchitectures, and a code example. The filter by CPU extension (SSE2, AVX2, AES-NI, etc.) makes it easy to find what's available at your target CPU level.
9. "A Guide to Vectorization with Intel C++ Compilers" Intel Corporation. Part of Intel Software Documentation
Explains how GCC and Clang (using Intel's vectorization techniques) auto-vectorize loops to use SSE/AVX instructions. Relevant context for understanding what the compiler generates in the SIMD register file and why. Includes examples of which loop patterns can be vectorized and which can't. Useful for the transition from understanding individual XMM/YMM registers to understanding how blocks of code use them.
10. CPUID Specification (Intel Manual Volume 2A, CPUID instruction entry) Intel Corporation. Part of the Software Developer's Manual
The exhaustive list of every CPUID leaf, sub-leaf, and bit, for every Intel CPU generation. When you need to detect a specific feature (beyond the common ones covered in this chapter), this is the reference. Organized by leaf value, with per-bit descriptions of EAX/EBX/ECX/EDX for each leaf. The online resource at felixcloutier.com/x86/cpuid mirrors this in a more searchable format.