Chapter 16 Quiz: ARM64 Architecture

Select the best answer for each question.

1. What does the acronym "RISC" stand for?

a) Rapid Instruction Set Computing b) Reduced Instruction Set Computer c) Register-Indexed Sequential Computing d) Reduced Instruction Set Cache

2. In ARM64, what is the name for the 32-bit view of the X5 register?

a) EX5 b) X5L c) W5 d) R5

3. You write the value 0xABCD to W0. What does X0 now contain?

a) 0xABCD (unchanged upper bits) b) 0x000000000000ABCD (zero-extended) c) 0xFFFFFFFF0000ABCD (sign-extended to 64 bits) d) 0xABCDABCDABCDABCD (replicated)

4. Which ARM64 instruction updates the condition flags?

a) ADD X0, X1, X2 b) ADDS X0, X1, X2 c) MOV X0, #42 d) LDR X0, [X1]

5. What does XZR always return when read?

a) The last written value b) The current stack pointer c) 0 d) An undefined value

6. ARM64's CMP X0, X1 is a pseudoinstruction. What does it actually assemble to?

a) SUB X0, X0, X1 b) SUBS X0, X0, X1 c) SUBS XZR, X0, X1 d) ANDS XZR, X0, X1

7. How long is every ARM64 instruction?

a) 1-4 bytes, depending on the instruction b) Always 2 bytes c) Always 4 bytes d) 4-8 bytes, depending on operand size

8. Which of the following is a valid ARM64 instruction? (All others are illegal)

a) ADD X0, X1, [X2] b) ADD X0, [X1], X2 c) ADD X0, X1, X2 d) ADD [X0], X1, X2

9. In ARM64, where is the return address stored after a BL instruction?

a) On the stack at [SP] b) In X30 (LR) c) In X29 (FP) d) In a hidden shadow register

10. What does AAPCS64 stand for?

a) Advanced Architecture Procedure Call Standard 64 b) ARM Application Procedure Call Standard for AArch64 c) Aligned ARM Process Call System 64-bit d) Advanced ARM Programming Convention Standard 64

11. In AAPCS64, which registers are callee-saved?

a) X0-X18 b) X0-X7 c) X19-X28 (plus X29 and X30) d) X9-X15

12. What ARM64 instruction is the equivalent of x86-64's CMOV (conditional move)?

a) CMOV b) MOVCC c) CSEL d) BSEL

13. Which instruction loads the program-counter-relative address of a label into X1?

a) MOV X1, label b) ADR X1, label c) LEA X1, [label] d) LDR X1, =label

14. On Linux ARM64, which register holds the system call number?

a) X0 b) X7 c) X8 d) X16

15. What instruction invokes a system call on Linux ARM64?

a) INT 0x80 b) SYSCALL c) SVC #0 d) TRAP #0

16. In ARM64, what happens when you write to a W register?

a) Only the lower 32 bits of the X register are updated; upper 32 bits are unchanged b) The upper 32 bits of the X register are zeroed c) The upper 32 bits of the X register are sign-extended d) The behavior is undefined

17. Which flag in PSTATE indicates that the result of an operation was negative?

a) Z (Zero) b) C (Carry) c) V (Overflow) d) N (Negative)

18. What is a key difference between the ARM64 C flag for subtraction vs. x86-64's carry flag for subtraction?

a) ARM64 doesn't have a carry flag b) They are identical c) ARM64 C=1 means no borrow; x86-64 CF=1 means borrow occurred d) ARM64 C=1 means borrow; x86-64 CF=0 means borrow occurred

19. ARM64 removed which ARM32 feature that allowed almost any instruction to be made conditional?

a) The link register b) The barrel shifter c) Per-instruction condition codes on all ALU operations d) The PSTATE flags

20. What is the minimum alignment requirement for the stack pointer (SP) when making a function call in AAPCS64?

a) 4 bytes b) 8 bytes c) 16 bytes d) 32 bytes