Chapter 9 Quiz: Arithmetic and Logic

Question 1. After mov rax, 0xFFFFFFFFFFFFFFFF; add rax, 1, which flags are set?

(A) OF = 1, CF = 0 (B) OF = 0, CF = 1, ZF = 1 (C) OF = 1, CF = 1, ZF = 1 (D) OF = 0, CF = 0, ZF = 1

Question 2. What does xor eax, eax accomplish, and why is it preferred over mov rax, 0?

(A) It sets EAX to 0 and also zeros the upper 32 bits of RAX; it is preferred because it has a shorter encoding and is recognized as a zero-idiom by the processor (B) It XORs EAX with itself, which always gives 1; it is a historical artifact with no practical benefit (C) It sets EAX to 0 but does not zero the upper 32 bits of RAX; it is slower than mov (D) It sets EAX to 0 and sets CF to 1

Question 3. Which instruction sign-extends RAX into RDX in preparation for a 64-bit IDIV?

(A) cdq (B) cqo (C) cwd (D) movsxd rdx, eax

Question 4. After div rbx, where do the quotient and remainder end up?

(A) Quotient in RDX, remainder in RAX (B) Quotient in RAX, remainder in RBX (C) Quotient in RAX, remainder in RDX (D) Quotient in RBX, remainder in RAX

Question 5. What is the key difference between INC and ADD with respect to flags?

(A) INC is faster but modifies more flags than ADD (B) INC does not modify CF; ADD does (C) ADD does not modify OF; INC does (D) INC only works on 8-bit registers; ADD works on all sizes

Question 6. The instruction test rax, 0xFF does which of the following?

(A) Loads the byte at address 0xFF into RAX (B) Tests whether any of the high 56 bits of RAX are set, setting ZF if they are all zero (C) Computes RAX & 0xFF, sets flags based on the result, but does not store the result anywhere (D) Stores the result of RAX & 0xFF into RAX

Question 7. What is the result of sar rax, 1 when RAX = 0x8000000000000000 (INT64_MIN)?

(A) 0x4000000000000000 (B) 0xC000000000000000 (C) 0x0000000000000001 (D) 0x8000000000000000 (unchanged because it cannot shift negative numbers)

Question 8. When multiplying two 64-bit values using the single-operand mul rbx, where is the result stored?

(A) In RBX only (truncated to 64 bits) (B) In RAX only (truncated to 64 bits) (C) In RDX:RAX (128-bit result, RDX=high, RAX=low) (D) In RAX:RBX (128-bit result, RAX=high, RBX=low)

Question 9. Which of the following correctly implements the C expression a % b for positive 64-bit signed integers a (in RAX) and b (in RBX)?

(A) div rbx; mov rax, rdx (B) cqo; idiv rbx; mov rax, rdx (C) xor rdx, rdx; div rbx — and the remainder is in RDX (D) xor rdx, rdx; idiv rbx

Question 10. The ADC instruction performs:

(A) dst = dst + src (identical to ADD) (B) dst = dst + src + CF (add with carry flag) (C) dst = dst + src + 1 (increment before add) (D) dst = dst AND src + CF

Question 11. What happens when the divisor in a DIV instruction is zero?

(A) The result is undefined and stored in RAX (B) RDX is set to 0 and RAX is set to 0 (C) CF is set to 1 to indicate the error (D) A #DE (Divide Error) exception is raised immediately

Question 12. After the instruction not rax, which flags are modified?

(A) ZF, SF, CF, OF (B) ZF only (C) No flags are modified (D) CF only (set to the previous MSB of RAX)

Question 13. Consider: mov rax, 0x7FFFFFFFFFFFFFFF; add rax, 1 Which statement is correct?

(A) CF = 1 because unsigned overflow occurred (B) OF = 1 because signed overflow occurred; CF = 0 because no unsigned overflow occurred (C) Both CF = 1 and OF = 1 (D) ZF = 1 because the result is zero

Question 14. (2 points) Write the assembly code to check whether a 64-bit value in RAX is odd (has bit 0 set), and jump to label odd_handler if it is. Do this without modifying RAX.

Question 15. In the three-operand form imul rax, rbx, 100, what does the instruction compute?

(A) rax = rax * rbx * 100 (triple multiply) (B) rax = rbx * 100 (the first operand is the destination, result is rbx × 100) (C) rax = rax * 100; rbx is ignored (D) rax = rbx + 100

Question 16. What is wrong with the following code for signed division by 4?

mov rax, -5
sar rax, 2    ; intended: rax = -5 / 4

(A) SAR cannot be used for negative values (B) SAR rounds toward negative infinity, so -5 >> 2 = -2, but C's -5/4 = -1 (C) The shift count is wrong; it should be sar rax, 1 (D) Nothing is wrong; this is exactly what GCC generates

Question 17. The cqo instruction is only needed before:

(A) Any signed multiply operation (B) The single-operand IDIV instruction (C) Any comparison involving negative numbers (D) The three-operand IMUL form

Question 18. Which of the following correctly computes rax = rdi * 3 using only LEA?

(A) lea rax, [rdi*3] (B) lea rax, [rdi + rdi*2] (C) lea rax, [rdi*2 + 1] (D) lea rax, [rdi + 3]

Question 19. (2 points) A loop uses the following sequence to detect 128-bit addition overflow:

add rax, [rsi]       ; add low halves
adc rdx, [rsi + 8]   ; add high halves with carry
jc  overflow         ; jump if carry from high-half addition

Is this correct? If not, what is the correct check?

Question 20. The MULX instruction (BMI2) differs from MUL in what important way?

(A) It performs signed multiplication instead of unsigned (B) It operates on 32-bit values instead of 64-bit (C) It does not modify any flags, making it suitable for pipelined multi-precision multiplication (D) It stores the result only in a single register (not RDX:RAX)