Chapter 19 Quiz: x86-64 vs. ARM64 Comparison

Select the best answer for each question.

1. What does modern x86-64 processors do internally that makes the CISC/RISC distinction less clear?

a) They compile x86-64 to RISC-V before execution b) They decode CISC instructions into RISC-like micro-operations (µops) before execution c) They run ARM64 code natively with a compatibility layer d) They execute instructions directly without decoding

2. ARM64 has 31 general-purpose registers. x86-64 has 16. For a function with 8 local variables, which architecture is less likely to need to spill variables to the stack?

a) x86-64, because its registers are faster b) ARM64, because it has more registers c) They are equal in practice d) x86-64, because it has the red zone

3. What is the primary reason ARM64's fixed-width 4-byte instructions are beneficial for the CPU decoder compared to x86-64's variable-width encoding?

a) Fixed-width instructions execute faster b) Fixed-width instructions are smaller in memory c) Fixed-width instructions eliminate the need to determine instruction boundaries before decoding d) Fixed-width instructions can be encrypted more easily

4. How does RISC-V handle conditional branches differently from both x86-64 and ARM64?

a) RISC-V has more condition codes than either architecture b) RISC-V combines comparison and branch into one instruction (BEQ, BNE, etc.) with no separate flags register c) RISC-V requires two instructions for every conditional branch d) RISC-V does not support conditional branches

5. ARM64's AAPCS64 calling convention uses how many integer argument registers?

a) 4 b) 6 c) 8 d) 10

6. What is Rosetta 2?

a) An ARM64 assembly language feature for converting integers b) Apple's ahead-of-time x86-64 to ARM64 binary translation layer c) A RISC-V emulator for Apple Silicon d) Apple's just-in-time compiler for Python

7. The Apple M1 achieved higher single-thread performance than competing Intel chips despite lower clock frequencies. Which of the following contributed to this?

a) M1 uses a different version of ARM64 that's incompatible with standard ARM64 code b) M1 benefits from simpler decoding (freeing die area for larger caches and wider execution) c) M1 uses a faster memory interface with DDR6 d) M1 executes x86-64 instructions natively in hardware

8. In a linked list traversal, ARM64 requires LDR W2, [X0] + ADD X1, X1, W2 to add a list element to a sum. x86-64 can do this in one instruction: add eax, [rdi]. This is because:

a) ARM64 is slower at arithmetic b) ARM64 uses a load/store architecture where ALU instructions cannot access memory c) ARM64's ADD instruction doesn't support 32-bit operands d) The x86-64 version is actually two micro-operations internally

9. Which statement about code density is most accurate?

a) x86-64 programs are always 50% smaller than equivalent ARM64 programs b) ARM64 programs are always larger, but typically by only 10-20% for real-world code c) ARM64 programs are always smaller because instructions are fixed-size d) Code size is identical because modern compilers optimize both equally

10. RISC-V's most significant distinction from ARM64 from an industry perspective is:

a) It has more registers b) It uses fixed-width encoding c) It is an open ISA with no licensing fees d) It has a weaker memory model

11. ARM64's barrel shifter allows ADD X0, X1, X2, LSL #3. What does x86-64 use instead to achieve the equivalent X0 = X1 + X2*8?

a) ADD RAX, [RBX + RCX*8] (SIB addressing — but only in memory context) b) LEA RAX, [RBX + RCX*8] (but only for address calculations in an LEA) c) There is no single instruction equivalent in x86-64 d) IMUL RCX, 8; ADD RAX, RBX (requires separate multiply)

12. In the data center, AWS Graviton (ARM64) offers approximately what price advantage over equivalent x86-64 instances?

a) 5% lower cost b) 25-35% lower cost for the same performance tier c) 50% lower cost d) They are priced identically

13. What memory ordering model does x86-64 use, and why does Rosetta 2 have to work around it?

a) WMO (Weak Memory Ordering) — stronger than ARM64 b) TSO (Total Store Order) — stronger than ARM64's model, requiring memory barriers in translation c) RMO (Relaxed Memory Ordering) — same as ARM64 d) MFENCE model — incompatible with all RISC architectures

14. ARM64's X30 (LR) holds the return address after a BL instruction. In x86-64, the equivalent information is:

a) Stored in RBP b) Pushed onto the stack by the CALL instruction c) Stored in a hidden shadow register d) Not stored (the programmer must save it manually)

15. A "Universal Binary" on macOS contains:

a) Both x86-64 and ARM64 code slices in one Mach-O file b) Code compiled for all operating systems (Windows, Linux, macOS) c) Both 32-bit and 64-bit ARM code d) Bytecode that runs on any architecture

16. For a function with 9 integer arguments on x86-64 (System V ABI), how many arguments are passed on the stack?

a) 0 (all in registers) b) 1 (the 9th argument — first 8 in registers, but x86-64 only has 6 arg regs) c) 3 (arguments 7, 8, and 9 — only 6 go in registers) d) 9 (all on the stack — System V always uses the stack)

17. The Apple M4 Firestorm cores have 192KB L1 instruction caches vs. Intel's typical 32KB. The primary benefit is:

a) Programs can be larger b) Hot code fits in L1 cache, eliminating cache misses for frequently executed functions c) Multiple programs can run simultaneously without switching d) The larger cache enables branch prediction

18. A developer compares: "x86-64 code for strcmp is ~40 bytes, ARM64 code is ~80 bytes." This 2× code size difference for ARM64 is PRIMARILY because:

a) ARM64 instructions are 4 bytes each b) ARM64 cannot fold memory access into comparison, requiring separate load instructions for each byte comparison c) ARM64 has fewer optimization passes in the compiler d) Both A and B contribute equally

19. Which ARM64 instruction does NOT have a direct one-instruction equivalent in x86-64 base ISA?

a) ADD X0, X1, X2 (three-register add) b) CMP X0, X1 (compare two registers) c) CSEL X0, X1, X2, EQ (conditional select between two different registers) d) B.EQ label (conditional branch)

20. As of 2026, approximately what percentage of new cloud instances sold are ARM64?

a) Less than 5% b) 10-15% c) 30-40% d) More than 70%