Chapter 3 Quiz: The x86-64 Architecture

17 questions covering registers, aliasing, calling conventions, RFLAGS, and architecture details.

Multiple Choice

1. After executing mov rax, 0xFFFFFFFF00000000 followed by mov eax, 0, what is the value of RAX?

A) 0xFFFFFFFF00000000 B) 0x0000000000000000 C) 0xFFFFFFFF00000000 with lower 32 bits cleared = 0xFFFFFFFF00000000 D) 0x00000000FFFFFFFF

2. In the System V AMD64 calling convention (Linux/macOS), the first six integer/pointer arguments are passed in which registers, in order?

A) RAX, RBX, RCX, RDX, RSI, RDI B) RDI, RSI, RDX, RCX, R8, R9 C) RCX, RDX, R8, R9, R10, R11 (this is the Windows calling convention) D) RAX, RDI, RSI, RDX, R8, R9

3. Which of the following registers must a function preserve (callee-save) in the System V AMD64 ABI?

A) RDI, RSI, RDX, RCX B) RAX, R10, R11 C) RBX, RBP, R12, R13, R14, R15 D) All registers must be preserved

4. The instruction movsx rax, bl does what?

A) Copies the 8-bit value in BL to RAX, zeroing the upper 56 bits B) Copies the 8-bit value in BL to RAX, sign-extending (filling upper bits with bit 7 of BL) C) Copies all 64 bits of RBX to RAX D) Copies the 8-bit value in BL to AL only

5. The SYSCALL instruction in x86-64 implicitly clobbers which two user-space registers?

A) RAX and RDX B) RSP and RBP C) RCX and R11 D) RDI and RSI

6. After executing mov rax, 0x0102030405060708 followed by mov ah, 0xFF, what is the value of RAX?

A) 0x01020304050607FF B) 0x01020304050607FF — wait, AH is bits 15:8, so: 0x010203040506FF08 C) 0x0102030405060708 (unchanged) D) 0x00000000000000FF

7. How many general-purpose 64-bit registers does x86-64 have?

A) 8 (the original x86 registers) B) 12 C) 16 D) 32

8. Which instruction pair correctly reads RFLAGS into RAX?

A) mov rax, rflags / mov rflags, rax B) lahf / sahf C) pushfq then pop rax D) mov rax, cr0 (control register 0 holds flags)

9. The CLD instruction:

A) Clears the Direction Flag (DF), causing string operations to increment SI/DI B) Sets the Direction Flag, causing string operations to decrement SI/DI C) Clears the Carry Flag D) Clears the Debug Flag

10. An SSE2 XMM register is how many bits wide?

A) 64 bits B) 128 bits C) 256 bits D) 512 bits

11. To detect whether the CPU supports AES-NI, you execute CPUID with EAX=1 and check which bit of which output register?

A) EAX bit 0 B) EBX bit 7 C) ECX bit 25 D) EDX bit 19

12. The REX.W prefix bit in an x86-64 instruction:

A) Extends the register field to access R8-R15 B) Forces the operation to use a 64-bit operand size C) Indicates a lock prefix is present D) Enables AVX instructions

True/False

13. Writing to AL (the low byte of RAX) in x86-64 automatically zeroes the upper 56 bits of RAX.

True / False

14. RIP (the instruction pointer) can be modified directly using a MOV rip, value instruction.

True / False

15. The FS and GS segment registers have their bases set to 0 in user-space 64-bit programs on Linux, and FS-relative memory accesses always access absolute address 0.

True / False

Short Answer

16. A function is called with rdi = 0xFFFFFFFF80000000 (a 64-bit value). Inside the function, the programmer writes:

mov  eax, edi    ; "copy the argument to return value"
ret

What value is actually returned in RAX? What value did the programmer likely intend to return? Explain the discrepancy.

17. Explain in two to three sentences why x86-64 has 16 general-purpose registers rather than 8 or 32. Include the historical reason why there were only 8 originally and the practical reason for not extending further.