Chapter 17 Quiz: ARM64 Instruction Set

Select the best answer for each question.

1. What does MADD X0, X1, X2, X3 compute?

a) X0 = X1 * X2 (and discard X3) b) X0 = X3 + X1 * X2 c) X0 = X3 * X1 + X2 d) X0 = (X1 + X2) * X3

2. You need the remainder of dividing X0 by X1 in ARM64. After SDIV X2, X0, X1, which instruction gives you the remainder in X3?

a) MOD X3, X0, X1 b) REM X3, X2, X1 c) MSUB X3, X2, X1, X0 d) SUB X3, X0, X2

3. What does ADD X0, X1, X2, LSL #3 compute?

a) X0 = X1 + X2 + 3 b) X0 = X1 + X2, then shift X0 left 3 c) X0 = X1 + (X2 << 3) d) X0 = (X1 + X2) << 3

4. What is BIC X0, X1, X2 equivalent to?

a) X0 = X1 AND X2 b) X0 = X1 AND NOT X2 c) X0 = NOT (X1 AND X2) d) X0 = X1 OR NOT X2

5. What addressing mode does LDR X0, [X1, #8]! use, and what happens to X1?

a) Post-indexed: X0 = Memory[X1], then X1 += 8 b) Pre-indexed: X1 += 8 first, then X0 = Memory[X1] c) Base+offset: X0 = Memory[X1 + 8], X1 unchanged d) Pre-indexed: X0 = Memory[X1], then X1 = 8

6. What does LDP X19, X20, [SP], #16 do?

a) X19 = Memory[SP]; X20 = Memory[SP+8]; SP += 16 after b) SP += 16; X19 = Memory[SP]; X20 = Memory[SP+8] c) X19 = Memory[SP]; X20 = Memory[SP+16]; SP unchanged d) SP += 16 first; X19 = Memory[SP]; X20 = Memory[SP+8]

7. In AAPCS64, which registers must a called function preserve (callee-saved)?

a) X0-X7 b) X8-X18 c) X19-X28, X29, X30 d) X9-X15

8. What is the range of an ARM64 B (unconditional branch) instruction?

a) ±4KB b) ±1MB c) ±128MB d) Any address (uses 64-bit encoding)

9. What is the ARM64 syscall number for write on Linux ARM64?

a) 1 b) 4 c) 64 d) 256

10. What does LDRSW X0, [X1] do?

a) Loads 64 bits from [X1] into X0 b) Loads 32 bits from [X1], zero-extends to 64 bits in X0 c) Loads 32 bits from [X1], sign-extends to 64 bits in X0 d) Loads 16 bits from [X1], sign-extends to 64 bits in X0

11. Which instruction would you use to branch to a function whose address is in register X5?

a) B X5 b) JMP X5 c) BLR X5 d) BR X5 (without saving return address)

12. In AAPCS64, before a function call (BL instruction), what alignment must SP have?

a) 4-byte alignment b) 8-byte alignment c) 16-byte alignment d) No alignment requirement

13. What does CBZ X0, label do?

a) Clears X0 then branches to label b) Branches to label if X0 equals zero (without modifying flags) c) Compares X0 to zero, sets flags, then branches if equal d) Branches to label always, storing X0 as return value

14. What does UMULH X2, X0, X1 compute?

a) X2 = unsigned(X0) * unsigned(X1) (lower 64 bits) b) X2 = the upper 64 bits of the 128-bit product X0 * X1 (unsigned) c) X2 = X0 * X1 / 2^64 d) X2 = max(X0, X1)

15. How does ARM64 RET differ from x86-64 RET?

a) ARM64 RET pops the return address from the stack b) ARM64 RET branches to the address in X30 (LR) c) ARM64 RET decrements SP then branches d) They are identical in behavior

16. What does TBNZ X0, #0, label do?

a) Branches to label if bit 0 of X0 is clear (zero) b) Branches to label if bit 0 of X0 is set (non-zero) c) Tests byte 0 of X0 and branches if not zero d) Branches to label if X0 is not zero (equivalent to CBNZ)

17. To load the 64-bit constant 0xDEAD000000000000 into X0 using the minimum number of instructions, you would use:

a) MOV X0, #0xDEAD000000000000 b) MOVZ X0, #0xDEAD, LSL #48 c) MOVZ X0, #0xDEAD followed by LSL X0, X0, #48 d) Three MOVK instructions

18. The canonical ARM64 function prologue STP X29, X30, [SP, #-16]! stores X29 at:

a) The original SP b) SP - 8 c) SP - 16 d) SP - 16 (new SP after pre-decrement)

19. Which of the following is NOT a valid ARM64 instruction?

a) ADD X0, X1, X2, LSL #3 b) LDR X0, [X1, X2, LSL #3] c) ADD X0, [X1], X2 d) CBZ X0, label

20. In the ARM64 Linux system call convention, which register holds the system call number?

a) X0 b) X7 c) X8 d) X16