Chapter 29 Quiz: Device I/O

1. What is the fundamental difference between port-mapped I/O and memory-mapped I/O?

A) Port-mapped I/O is faster; memory-mapped I/O is more compatible B) Port-mapped I/O uses IN/OUT instructions and a separate 16-bit address space; MMIO uses MOV instructions and regular memory addresses C) Port-mapped I/O requires ring 0; memory-mapped I/O is accessible in ring 3 D) Port-mapped I/O is for read-only devices; MMIO is for read-write devices

Answer: B — Port-mapped I/O (PMIO) uses the dedicated I/O address space and the IN/OUT instructions (which are also privileged in ring 0). Memory-mapped I/O (MMIO) places device registers in the physical address space, accessed with ordinary MOV instructions.

2. What is the PIT's internal oscillator frequency?

A) 1 MHz B) 1.193182 MHz C) 14.318 MHz D) 3.58 MHz

Answer: B — The 8253/8254 PIT uses a 1.193182 MHz clock derived from the original IBM PC's 14.318 MHz crystal (÷12). This odd frequency is why PIT divisors for common rates are not round numbers.

3. To configure the PIT for 100Hz interrupts, what reload value (divisor) should be written to the counter?

A) 100 B) 1000 C) 11,931 D) 65,535

Answer: C — Divisor = 1,193,182 / 100 = 11,931 (approximately). The PIT counts down at 1.193182 MHz; when it reaches 0, it fires IRQ0 and reloads.

4. What sequence is required to write a 16-bit divisor to PIT Channel 0?

A) Write the entire 16-bit value as a single OUT instruction B) Write low byte first (to port 0x40), then high byte (to port 0x40) C) Write high byte first (to port 0x40), then low byte (to port 0x41) D) Write to port 0x43 once with all bits set

Answer: B — After setting Access Mode = 11 (lo+hi) in the Mode/Command register (port 0x43), you write the low byte then the high byte sequentially to the channel port (0x40 for Channel 0). The PIT accepts them in this order.

5. What is the base I/O port address for COM1 (first serial port)?

A) 0x2F8 B) 0x3E8 C) 0x3F8 D) 0x4F8

Answer: C — COM1 is at 0x3F8 through 0x3FF (8 registers). COM2 is at 0x2F8. COM3 at 0x3E8, COM4 at 0x2E8.

6. Before writing a character to the UART transmit register, what must you check?

A) That the receive buffer is empty B) That the Transmitter Holding Register Empty bit (bit 5 of Line Status Register) is set C) That the data ready bit is set D) That the modem is connected and CTS is asserted

Answer: B — Bit 5 of the Line Status Register (at port base+5) indicates that the Transmitter Holding Register (THR) is empty and ready to accept a new character. Writing before this bit is set corrupts the previous character being transmitted.

7. At what physical address is the Local APIC (LAPIC) memory-mapped by default?

A) 0x000A0000 B) 0xFEE00000 C) 0xFFFF0000 D) 0x00100000

Answer: B — The Local APIC is mapped at physical address 0xFEE00000 by default. This can be relocated via the IA32_APIC_BASE MSR, but 0xFEE00000 is the standard location used by virtually all systems.

8. What does writing 0 to the LAPIC EOI register (offset 0x0B0) accomplish?

A) Disables all future interrupts from the LAPIC B) Signals to the LAPIC that the current interrupt has been processed, allowing the next one C) Resets the LAPIC to its default state D) Acknowledges the interrupt to the originating I/O APIC

Answer: B — The LAPIC EOI (End of Interrupt) write signals completion of the current interrupt service routine. Without it, the LAPIC will not deliver the next interrupt of equal or lower priority. This is the LAPIC equivalent of the PIC's EOI command.

9. To read PCI device configuration space, which two I/O ports are used?

A) 0x2E8 (address) and 0x2EC (data) B) 0xCF8 (address) and 0xCFC (data) C) 0x3C0 (address) and 0x3C4 (data) D) 0xF0 (address) and 0xF4 (data)

Answer: B — Port 0xCF8 is the PCI Configuration Address register; write the 32-bit address (bus/device/function/offset + enable bit 31) here. Port 0xCFC is the PCI Configuration Data register; read or write 32 bits of configuration data here.

10. Why does ARM64 require explicit memory barriers (DSB/DMB) for MMIO access, while x86-64 generally does not?

A) ARM64 has a weaker memory ordering model that allows more MMIO access reordering B) ARM64 MMIO registers are farther away in the address space C) x86-64 has hardware that automatically detects MMIO regions D) ARM64 uses a different physical address space for device registers

Answer: A — ARM64's memory model allows significant reordering of memory accesses (it is a "weakly ordered" architecture). MMIO accesses to device registers can be reordered with each other or with normal memory accesses, causing incorrect device behavior. x86-64 has a stronger ordering model (TSO) that prevents most harmful reorderings for I/O.

11. What is the purpose of writing 0x80 to the UART Line Control Register (LCR, port base+3)?

A) Enable the FIFO buffer for 128-byte capacity B) Set the DLAB (Divisor Latch Access Bit) to allow writing the baud rate divisor C) Reset the UART to its default state D) Configure 8 data bits, no parity

Answer: B — Setting bit 7 (DLAB) of the LCR allows access to the divisor latch registers at offsets +0 and +1 (which normally serve as data and interrupt enable registers). After writing the divisor, clear DLAB to restore normal operation.

12. The io_wait function often writes to port 0x80. Why is port 0x80 used?

A) It is the fastest port to write to B) Port 0x80 is the POST diagnostic port — writes to it are safe and cause a brief delay C) Port 0x80 triggers an NMI when written D) It is the port for accessing the system timer

Answer: B — Port 0x80 is the POST (Power-On Self Test) diagnostic port, originally used to display status codes during boot. Writing to it is harmless and causes a short bus cycle that provides the I/O delay needed by older ISA devices. Most modern hardware doesn't need this delay.

13. In the UART 16550, what does the acronym "8N1" describe?

A) 8-bit bus, no NMI, 1 IRQ B) 8 data bits, No parity, 1 stop bit C) 8 MHz clock, Normal speed, 1 byte buffer D) 8 port addresses, None reserved, 1 device

Answer: B — 8N1 is the standard serial port configuration: 8 data bits per character, No parity bit, 1 stop bit. This gives 10 bits per character (1 start + 8 data + 1 stop), so at 115200 baud, the throughput is 11,520 characters per second.

14. Which PIT operating mode generates a periodic square wave useful for a system timer?

A) Mode 0 (Interrupt on Terminal Count) — fires once B) Mode 2 (Rate Generator) — periodic low pulse C) Mode 3 (Square Wave Generator) — periodic, even duty cycle D) Mode 4 (Software Triggered Strobe) — fires on write

Answer: C — Mode 3 (Square Wave Generator) generates a periodic square wave: output is high for half the count, then low for half the count, then reloads and repeats. This provides a clean, periodic IRQ0. Mode 2 also provides periodic interrupts but with a different duty cycle.

15. What value is returned by reading PCI configuration space vendor ID from a slot with no device installed?

A) 0x0000 B) 0x1234 (default PCI vendor) C) 0xFFFF D) 0x8086 (Intel)

Answer: C — When no device is present at a bus/device/function address, the PCI bus returns all-ones: 0xFFFFFFFF for a 32-bit read, so the vendor ID (low 16 bits) reads as 0xFFFF. PCI code always checks for 0xFFFF to skip empty slots.