Chapter 8 Further Reading: Data Movement and Addressing Modes

Primary References

Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 2: Instruction Set Reference Intel Corporation. Available free at intel.com/sdm. The definitive reference for every instruction encoding. Volume 2A covers instructions A-M, Volume 2B covers N-Z. For MOV: look up the 30+ separate encodings (MOV r/m8,r8; MOV r/m16,r16; MOV r64,imm64; etc.). For LEA: the description of the effective address computation. The "Description" and "Operation" pseudocode sections for each instruction are authoritative.

AMD64 Architecture Programmer's Manual, Volume 3: General-Purpose and System Instructions AMD, Inc. Available at developer.amd.com. AMD's reference covers the same instructions with slightly different phrasing. Worth consulting when Intel's wording is ambiguous. Volume 1 (Application Programming) has a useful high-level overview of the addressing mode encoding in the ModRM/SIB byte format.

Architecture and Encoding

"x86 Instruction Encoding" — OSDev Wiki (wiki.osdev.org/X86-64_Instruction_Encoding) The most accessible explanation of how ModRM, SIB, REX, and displacement bytes work together to encode every addressing mode. Understanding the encoding is not required for using the instructions, but it explains why RSP cannot be an index register (it is used as an escape code in the SIB byte) and why certain combinations require longer encodings.

"Intel x86 Encoding Cheat Sheet" — Scott Wolchok A compact reference for the instruction encoding format. Useful if you ever need to manually decode bytes from a memory dump or write a disassembler.

Compiler Code Generation

GCC Internals: RTL Generation and the MD Files gcc.gnu.org/onlinedocs/gccint/ The GCC internals documentation explains how the compiler selects instruction patterns, including the peephole2 optimizations that replace IMUL with LEA+SHL sequences. Relevant chapter: "Machine Descriptions."

"Optimizing subroutines in assembly language" — Agner Fog agner.org/optimize/optimizing_assembly.pdf Chapter 16 covers LEA and address generation extensively. Agner Fog's optimization manuals are the standard reference for x86 performance tuning. The "Instruction tables" document (separate PDF) gives the exact latency and throughput for every instruction on every Intel/AMD microarchitecture.

Godbolt Compiler Explorer — godbolt.org The indispensable tool for understanding what a compiler does with C code. Enter a C function, select GCC x86-64 with -O2, and see the assembly output immediately. Essential for verifying the LEA patterns described in this chapter.

Performance

"Intel 64 and IA-32 Architectures Optimization Reference Manual" Intel Corporation (intel.com, document 248966). Chapter 3 covers the execution engine and address generation units. Section 3.5 discusses the latency of complex addressing modes. This is the authoritative source for the "1 cycle for all addressing modes on Haswell+" claim.

"Microarchitecture" documentation — Agner Fog (agner.org/optimize/microarchitecture.pdf) Detailed per-microarchitecture analysis. The sections on Intel Sandy Bridge, Haswell, and Skylake explain the AGU (Address Generation Unit) pipeline and why the four-component addressing mode was cheaper on Haswell than on Sandy Bridge.

Practical Tools

GDB with Intel Syntax

echo "set disassembly-flavor intel" >> ~/.gdbinit

Makes all GDB disassembly use Intel syntax (matching NASM). The default AT&T syntax is unnecessarily confusing for programmers coming from NASM. Setting this globally saves constant cognitive overhead.

objdump Disassembly

objdump -d -M intel your_binary

The -M intel flag switches to Intel syntax. Use this to inspect the compiled output of C programs and compare to your hand-written assembly.