Chapter 14 Quiz: Floating Point

Question 1. Which instruction is used for scalar double-precision floating-point addition in SSE2?

(A) faddl (B) addsd (C) addpd (D) addss

Question 2. CVTTSD2SI rax, xmm0 with XMM0 = 3.7 gives:

(A) 4 (rounds to nearest) (B) 3 (truncates toward zero) (C) 3 (rounds toward -inf) (D) -3 (sign error)

Question 3. The MXCSR register controls:

(A) x87 FPU exception behavior only (B) SSE/AVX floating-point exception masks, rounding mode, and denormal handling (C) Whether SIMD instructions use 128-bit or 256-bit operands (D) The size of XMM registers

Question 4. After UCOMISD xmm0, xmm1 where XMM0 = NaN, what are the flags?

(A) ZF=1, CF=0, PF=0 (equal) (B) ZF=0, CF=1, PF=0 (less than) (C) ZF=1, CF=1, PF=1 (unordered — indicates NaN involved) (D) OF=1 (overflow flag set for NaN)

Question 5. The main reason x87 is avoided in modern code is:

(A) It is slower than SSE for all operations (B) It cannot compute square roots (C) The stack-based model is error-prone and does not support SIMD parallelism (D) It is not available in 64-bit mode

Question 6. MOVSS xmm0, [rbx] loads:

(A) 128 bits from [rbx] into XMM0 (B) 32 bits from [rbx] into XMM0[31:0]; zeros XMM0[127:32] (C) 64 bits from [rbx] into XMM0[63:0]; zeros XMM0[127:64] (D) 32 bits from [rbx] into XMM0[31:0]; preserves XMM0[127:32]

Question 7. Why should you almost never compare floating-point values with exact equality (je after UCOMISD)?

(A) JE does not work after UCOMISD (B) Floating-point arithmetic involves rounding errors, so mathematically equal values often differ in their binary representations (C) UCOMISD does not set ZF correctly for equal values (D) The IEEE standard prohibits equality comparison of floats

Question 8. The Flush-to-Zero (FTZ) bit in MXCSR, when set, causes:

(A) Overflow results to be flushed to ±MAX_FLOAT instead of ±Infinity (B) Denormal results to be replaced with zero, avoiding the performance penalty of denormal microcode (C) NaN to be replaced with zero (D) Division by zero to produce zero instead of Infinity

Question 9. SQRTSD xmm0, xmm1 computes:

(A) The square root of all four doubles in XMM1, stored to XMM0 (B) The square root of XMM1[63:0] (the low double), stored to XMM0[63:0]; XMM0[127:64] is zeroed or unchanged (C) The reciprocal of XMM1 (D) XMM0 = XMM0 * XMM1 (multiply not square root — SD means "scaled double")

Question 10. Which conversion instruction correctly implements C's (int64_t)double_value cast (truncate toward zero)?

(A) cvtsd2si rax, xmm0 (B) cvttsd2si rax, xmm0 (C) cvtsi2sd xmm0, rax (D) cvtsd2ss xmm0, xmm1

Question 11. The x87 instruction FSINCOS is useful because:

(A) It computes both sin and cos in less time than two separate calls (B) It is the only way to compute sin in x86-64 (C) It stores results in a non-stack register, making them easier to use (D) It is available on all SSE processors and does not require x87

Question 12. IEEE 754 infinity arithmetic: (+∞) + (-∞) equals:

(A) 0.0 (B) +∞ (C) -∞ (D) NaN (indeterminate form)

Question 13. A NaN value compared with itself using UCOMISD xmm0, xmm0 (same register) gives:

(A) ZF=1, PF=0 (equal, since it's the same register) (B) ZF=1, CF=1, PF=1 (unordered — NaN is not equal to itself, NaN != NaN) (C) ZF=0, CF=0 (neither equal nor less) (D) This is undefined behavior

Question 14. (2 points) Write the NASM SSE2 code to convert a 32-bit integer in EDI to a single-precision float in XMM0.

Question 15. ADDSS xmm0, xmm1 versus ADDPS xmm0, xmm1 — the key difference is:

(A) ADDSS requires 32-bit alignment; ADDPS does not (B) ADDSS adds only the low 32-bit float; ADDPS adds all four 32-bit floats in the 128-bit register simultaneously (C) ADDSS is for x87; ADDPS is for SSE (D) ADDPS is faster than ADDSS when only one float is needed

Question 16. The ROUNDSD xmm0, xmm1, 9 instruction (immediate = 9 = 0b1001) computes:

(A) Round xmm1 to nearest integer (ties to even), using the rounding mode from the immediate (B) Round xmm1 toward -infinity (floor) (C) Truncate xmm1 toward zero (D) Round toward +infinity (ceil)

Question 17. Why does 0.1 + 0.2 != 0.3 in floating-point arithmetic?

(A) The + operator adds 1 bit of error per operation (B) 0.1, 0.2, and 0.3 cannot be represented exactly in binary floating-point; their approximations introduce rounding errors that accumulate (C) IEEE 754 defines + to round toward zero, not to nearest (D) This is a compiler bug specific to certain optimization levels

Question 18. The x87 FPU register stack has how many 80-bit registers?

(A) 4 (B) 6 (C) 8 (D) 16

Question 19. In the System V AMD64 ABI, floating-point function arguments are passed in:

(A) The integer registers (RDI, RSI, RDX, ...) (B) XMM0-XMM7 (first 8 float/double arguments) (C) XMM0-XMM5 (first 6 float/double arguments) (D) Pushed on the stack in all cases

Question 20. A program encounters sudden 40-100× slowdowns on certain inputs. The inputs are very small positive double values (close to 0, below 2.2×10^-308). The most likely cause is:

(A) Cache misses for the small values (B) Denormal (subnormal) number handling, which triggers microcode and costs 40-150 extra cycles per operation (C) Floating-point overflow to NaN (D) Division by zero producing Infinity, which is slow to process