Chapter 8 Quiz: Data Movement and Addressing Modes

Instructions: Each question is worth 1 point unless marked otherwise. For multiple-choice questions, choose the single best answer.

Question 1. After the instruction mov eax, 0x12345678, what is the value of the full 64-bit register RAX, assuming RAX previously contained 0xFFFFFFFFFFFFFFFF?

(A) 0xFFFFFFFF12345678 (B) 0x0000000012345678 (C) 0x12345678FFFFFFFF (D) 0x123456780000FFFF

Question 2. Which of the following is a valid x86-64 scale factor for the index component of an addressing mode?

(A) 3 (B) 6 (C) 4 (D) 16

Question 3. The instruction lea rax, [rbx + rcx*4 + 8]:

(A) Loads a 4-byte value from the address rbx + rcx*4 + 8 into RAX (B) Computes the value rbx + rcx*4 + 8 and stores it in RAX without any memory access (C) Stores RAX into memory at address rbx + rcx*4 + 8 (D) Is invalid because LEA cannot use a displacement

Question 4. A memory location contains the byte value 0xF0. After movsx rax, byte [rbx], what is the value of RAX?

(A) 0x00000000000000F0 (B) 0xFFFFFFFFFFFFFFF0 (C) 0x000000000000F000 (D) 0xF000000000000000

Question 5. Which register CANNOT be used as the index register in an x86-64 addressing mode?

(A) RBX (B) RSP (C) R12 (D) RBP

Question 6. What is the key difference between mov al, [rbx] and movzx rax, byte [rbx]?

(A) Both are identical in effect (B) mov al, [rbx] preserves bits 63:8 of RAX; movzx rax, byte [rbx] zeroes them (C) movzx sign-extends while mov al zero-extends (D) mov al, [rbx] is faster because it has a shorter encoding

Question 7. Given int64_t arr[10], with the base address in RDI and an index in RCX, which instruction correctly accesses arr[rcx]?

(A) mov rax, [rdi + rcx] (B) mov rax, [rdi + rcx*4] (C) mov rax, [rdi + rcx*8] (D) mov rax, [rdi*rcx + 8]

Question 8. What is the result in RAX after:

mov rbx, 7
lea rax, [rbx + rbx*2]

(A) 14 (B) 21 (C) 28 (D) 49

Question 9. RIP-relative addressing is used in 64-bit code primarily because:

(A) It is faster than absolute addressing (B) 64-bit absolute addresses don't fit in most instruction encodings, and it enables position-independent code (C) It provides automatic bounds checking (D) It is the only addressing mode that works in 64-bit mode

Question 10. The memory form of xchg (e.g., xchg [mutex], rax) has what important property?

(A) It requires an explicit LOCK prefix to be atomic (B) It is always atomic, even without an explicit LOCK prefix (C) It is not available in 64-bit mode (D) It only works with byte operands

Question 11. After the instruction sequence:

mov rax, 0x1234567890ABCDEF
mov ax, 0xFFFF

What is the value of RAX?

(A) 0x000000000000FFFF (B) 0x1234567890ABFFFF (C) 0xFFFF567890ABCDEF (D) 0xFFFFFFFFFFFFFFFF

Question 12. (2 points) A struct Employee has the following layout:

struct Employee {
    uint32_t id;        // offset 0
    uint32_t dept;      // offset 4
    int64_t  salary;    // offset 8
    char    *name;      // offset 16
};

Register RDI holds a pointer to an Employee. Write the NASM instruction to load the salary field into RSI.

Question 13. Which of the following correctly multiplies RDI by 12 using only LEA and SHL?

(A)

lea rax, [rdi*12]

(B)

lea rax, [rdi + rdi*2]
shl rax, 2

(C)

lea rax, [rdi*4]
lea rax, [rax*3]

(D)

lea rax, [rdi + rdi*4]
shl rax, 2

Question 14. What is the primary reason MOV from memory to memory is not supported as a single instruction?

(A) It would be too slow (B) The instruction encoding only has room for one memory address operand (C) Memory-to-memory operations are not needed in practice (D) It would require two separate cache accesses

Question 15. In AT&T syntax, movq 8(%rbx,%rcx,4), %rax is equivalent to which NASM instruction?

(A) mov rax, [rbx + rcx*4 + 8] (B) mov rax, [rcx + rbx*4 + 8] (C) mov rax, [rbx*4 + rcx + 8] (D) mov [rbx + rcx*4 + 8], rax

Question 16. A 32-bit integer value at [rdi] contains -1 (0xFFFFFFFF). After movsxd rax, dword [rdi], what is the value of RAX?

(A) 0x00000000FFFFFFFF (B) 0xFFFFFFFFFFFFFFFF (C) 0xFFFFFFFF00000000 (D) 0x0000000000000001

Question 17. What is the value of RBX after:

mov rbx, 0x1234567890ABCDEF
mov ebx, ebx

(A) 0x1234567890ABCDEF (B) 0x000000000ABCDEF (C) 0x0000000090ABCDEF (D) Same as the second line is not valid

Question 18. Which of the following uses of LEA does NOT access memory?

(A) lea rax, [rbx] — loads the value stored at address RBX into RAX (B) lea rax, [rbx + 8] — computes RBX+8, stores in RAX, no memory access (C) LEA always accesses memory; that is its purpose (D) LEA and MOV are identical for register-indirect addressing

Question 19. (2 points) Explain why lea rcx, [rcx + 1] might be preferred over inc rcx in certain performance-critical inner loops. Your answer should reference the specific processor resource these instructions compete for.

Question 20. Given the instruction mov rax, [rel global_var] where global_var is in the .data section, the address is computed as:

(A) The absolute 64-bit address stored in the instruction encoding (B) RIP plus a 32-bit signed offset encoded in the instruction (C) RBP plus the offset of global_var (D) The address stored in RSI at the time of execution